#ifndef __ZDHW_C__
#define __ZDHW_C__

#include "zdtypes.h"
#include "zdequates.h"
#include "zdapi.h"
#include "zdhw.h"
#include "zddebug.h"
#include "zd1211.h"
#include "zd1205.h"
#include "zdglobal.h"
extern struct net_device *g_dev;
extern u8 mMacMode;
extern u8 *mTxOFDMType;
#if ZDCONF_80211A_SUPPORT == 1
extern const U16 dot11A_Channel[];
extern const U16 dot11A_Channel_Amount;
extern u8 a_OSC_get_cal_int( u8 ch, u32 rate, u8 *intValue, u8 *calValue); 
#endif

u8 LastSetChannel=1;
u8 LastMacMode=0;
/*
U32 GRF5101T[] = {
    0x1A0000,   //Null 
    0x1A0000,   //Ch 1
    0x1A8000,   //Ch 2
    0x1A4000,   //Ch 3
    0x1AC000,   //Ch 4
    0x1A2000,   //Ch 5
    0x1AA000,   //Ch 6
    0x1A6000,   //Ch 7
    0x1AE000,   //Ch 8
    0x1A1000,   //Ch 9
    0x1A9000,   //Ch 10
    0x1A5000,   //Ch 11
    0x1AD000,   //Ch 12
    0x1A3000,   //Ch 13
    0x1AB000    //Ch 14
};


U32 AL2210TB[] = {
    0x2396c0,   //;Null 
    0x0196c0,   //;Ch 1
    0x019710,   //;Ch 2
    0x019760,   //;Ch 3
    0x0197b0,   //;Ch 4
    0x019800,   //;Ch 5
    0x019850,   //;Ch 6
    0x0198a0,   //;Ch 7
    0x0198f0,   //;Ch 8
    0x019940,   //;Ch 9
    0x019990,   //;Ch 10
    0x0199e0,   //;Ch 11
    0x019a30,   //;Ch 12
    0x019a80,   //;Ch 13
    0x019b40    //;Ch 14
};


U32	M2827BF[] = {
    0x0ccd4,    //;Null 
    0x0ccd4,    //;Ch 1
    0x22224,    //;Ch 2
    0x37774,    //;Ch 3
    0x0ccd4,    //;Ch 4
    0x22224,    //;Ch 5
    0x37774,    //;Ch 6
    0x0ccd4,    //;Ch 7
    0x22224,    //;Ch 8
    0x37774,    //;Ch 9
    0x0ccd4,    //;Ch 10
    0x22224,    //;Ch 11
    0x37774,    //;Ch 12
    0x0ccd4,    //;Ch 13
    0x199a4    //;Ch 14
};


U32	M2827BN[] = {
    0x30a03,    //;Null 
    0x30a03,    //;Ch 1
    0x00a13,    //;Ch 2
    0x10a13,    //;Ch 3
    0x30a13,    //;Ch 4
    0x00a23,    //;Ch 5
    0x10a23,    //;Ch 6
    0x30a23,    //;Ch 7
    0x00a33,    //;Ch 8
    0x10a33,    //;Ch 9
    0x30a33,    //;Ch 10
    0x00a43,    //;Ch 11
    0x10a43,    //;Ch 12
    0x30a43,    //;Ch 13
    0x20a53    //;Ch 14
};


U32	M2827BF2[] = {
    0x33334,    //;Null 
    0x33334,    //;Ch 1
    0x08884,    //;Ch 2
    0x1ddd4,    //;Ch 3
    0x33334,    //;Ch 4
    0x08884,    //;Ch 5
    0x1ddd4,    //;Ch 6
    0x33334,    //;Ch 7
    0x08884,    //;Ch 8
    0x1ddd4,    //;Ch 9
    0x33334,    //;Ch 10
    0x08884,    //;Ch 11
    0x1ddd4,    //;Ch 12
    0x33334,    //;Ch 13
    0x26664    //;Ch 14
};

U32	M2827BN2[] = {
    0x10a03,    //;Null 
    0x10a03,    //;Ch 1
    0x20a13,    //;Ch 2
    0x30a13,    //;Ch 3
    0x10a13,    //;Ch 4
    0x20a23,    //;Ch 5
    0x30a23,    //;Ch 6
    0x10a23,    //;Ch 7
    0x20a33,    //;Ch 8
    0x30a33,    //;Ch 9
    0x10a33,    //;Ch 10
    0x20a43,    //;Ch 11
    0x30a43,    //;Ch 12
    0x10a43,    //;Ch 13
    0x20a53    //;Ch 14
};
*/
 //OFDM
#if ZDCONF_RF_UW2453_SUPPORT == 1
U32 UW2453RF_dongle[][45] = { 
	//talbe 1
	{
		0x100047, 0x200999, 0x34664D,   //;Null 
		0x100047, 0x200999, 0x34664D,   //;Ch 1		2412
		0x100047, 0x20099b, 0x34664D,   //;Ch 2		2417
		0x100067, 0x200998, 0x34664D,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34664D,	//;Ch 4		2427
		0x100067, 0x200999, 0x346675,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346675,	//;Ch 6		2437
		0x100057, 0x200998, 0x346675,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346675,	//;Ch 8		2447
		0x100057, 0x200999, 0x346655,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346655,	//;Ch 10	2457
		0x100077, 0x200998, 0x346655,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346655,	//;Ch 12	2467
		0x100077, 0x200999, 0x346665,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346665	//;Ch 14	2484 
	},
	//talbe 2
	{
		0x100047, 0x200999, 0x34666D,   //;Null 
		0x100047, 0x200999, 0x34666D,   //;Ch 1		2412
		0x100047, 0x20099b, 0x34666D,   //;Ch 2		2417
		0x100067, 0x200998, 0x34666D,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34666D,	//;Ch 4		2427
		0x100067, 0x200999, 0x34664D,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34664D,	//;Ch 6		2437
		0x100057, 0x200998, 0x34664D,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34664D,	//;Ch 8		2447
		0x100057, 0x200999, 0x346675,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346675,	//;Ch 10	2457
		0x100077, 0x200998, 0x346675,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346675,	//;Ch 12	2467
		0x100077, 0x200999, 0x346655,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346655	//;Ch 14	2484 
	},
	//talbe 3
	{
		0x100047, 0x200999, 0x34665D,   //;Null 
		0x100047, 0x200999, 0x34665D,   //;Ch 1		2412
		0x100047, 0x20099b, 0x34665D,   //;Ch 2		2417
		0x100067, 0x200998, 0x34665D,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34665D,	//;Ch 4		2427
		0x100067, 0x200999, 0x34666D,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34666D,	//;Ch 6		2437
		0x100057, 0x200998, 0x34666D,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34666D,	//;Ch 8		2447
		0x100057, 0x200999, 0x34664D,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34664D,	//;Ch 10	2457
		0x100077, 0x200998, 0x34664D,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34664D,	//;Ch 12	2467
		0x100077, 0x200999, 0x346675,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346675	//;Ch 14	2484 
	},
	//table 4
	{
		0x100047, 0x200999, 0x34667D,	//;Null 
		0x100047, 0x200999, 0x34667D,   //;Ch 1		2412
		0x100047, 0x20099b, 0x34667D,   //;Ch 2		2417
		0x100067, 0x200998, 0x34667D,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34667D,	//;Ch 4		2427
		0x100067, 0x200999, 0x34665D,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34665D,	//;Ch 6		2437
		0x100057, 0x200998, 0x34665D,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34665D,	//;Ch 8		2447
		0x100057, 0x200999, 0x34666D,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34666D,	//;Ch 10	2457
		0x100077, 0x200998, 0x34666D,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34666D,	//;Ch 12	2467
		0x100077, 0x200999, 0x34664D,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x34664D	//;Ch 14	2484 
	},
	//table 5
	{
		0x100047, 0x200999, 0x346643,   //;Null 
		0x100047, 0x200999, 0x346643,   //;Ch 1		2412
		0x100047, 0x20099b, 0x346643,   //;Ch 2		2417
		0x100067, 0x200998, 0x346643,	//;Ch 3		2422
		0x100067, 0x20099a, 0x346643,	//;Ch 4		2427
		0x100067, 0x200999, 0x34667D,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34667D,	//;Ch 6		2437
		0x100057, 0x200998, 0x34667D,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34667D,	//;Ch 8		2447
		0x100057, 0x200999, 0x34665D,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34665D,	//;Ch 10	2457
		0x100077, 0x200998, 0x34665D,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34665D,	//;Ch 12	2467
		0x100077, 0x200999, 0x34666D,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x34666D	//;Ch 14	2484 
	},
	//table 6
	{
		0x100047, 0x200999, 0x346663,   //;Null 
		0x100047, 0x200999, 0x346663,   //;Ch 1		2412
		0x100047, 0x20099b, 0x346663,   //;Ch 2		2417
		0x100067, 0x200998, 0x346663,	//;Ch 3		2422
		0x100067, 0x20099a, 0x346663,	//;Ch 4		2427
		0x100067, 0x200999, 0x346643,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346643,	//;Ch 6		2437
		0x100057, 0x200998, 0x346643,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346643,	//;Ch 8		2447
		0x100057, 0x200999, 0x34667D,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34667D,	//;Ch 10	2457
		0x100077, 0x200998, 0x34667D,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34667D,	//;Ch 12	2467
		0x100077, 0x200999, 0x34665D,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x34665D	//;Ch 14	2484 
	},
	//table 7
	{
		0x100047, 0x200999, 0x346653,   //;Null 
		0x100047, 0x200999, 0x346653,   //;Ch 1		2412
		0x100047, 0x20099b, 0x346653,   //;Ch 2		2417
		0x100067, 0x200998, 0x346653,	//;Ch 3		2422
		0x100067, 0x20099a, 0x346653,	//;Ch 4		2427
		0x100067, 0x200999, 0x346663,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346663,	//;Ch 6		2437
		0x100057, 0x200998, 0x346663,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346663,	//;Ch 8		2447
		0x100057, 0x200999, 0x346643,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346643,	//;Ch 10	2457
		0x100077, 0x200998, 0x346643,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346643,	//;Ch 12	2467
		0x100077, 0x200999, 0x34667D,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x34667D	//;Ch 14	2484 
	},
	//table 8
	{
		0x100047, 0x200999, 0x346673,   //;Null 
		0x100047, 0x200999, 0x346673,   //;Ch 1		2412
		0x100047, 0x20099b, 0x346673,   //;Ch 2		2417
		0x100067, 0x200998, 0x346673,	//;Ch 3		2422
		0x100067, 0x20099a, 0x346673,	//;Ch 4		2427
		0x100067, 0x200999, 0x346653,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346653,	//;Ch 6		2437
		0x100057, 0x200998, 0x346653,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346653,	//;Ch 8		2447
		0x100057, 0x200999, 0x346663,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346663,	//;Ch 10	2457
		0x100077, 0x200998, 0x346663,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346663,	//;Ch 12	2467
		0x100077, 0x200999, 0x346643,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346643	//;Ch 14	2484 
	},
	//table 9
	{
		0x100047, 0x200999, 0x34664B,   //;Null 
		0x100047, 0x200999, 0x34664B,	//;Ch 1		2412
		0x100047, 0x20099b, 0x34664B,   //;Ch 2		2417
		0x100067, 0x200998, 0x34664B,	//;Ch 3	    2422
		0x100067, 0x20099a, 0x34664B,	//;Ch 4		2427
		0x100067, 0x200999, 0x346673,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346673,	//;Ch 6		2437
		0x100057, 0x200998, 0x346673,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346673,	//;Ch 8		2447
		0x100057, 0x200999, 0x346653,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346653,	//;Ch 10	2457
		0x100077, 0x200998, 0x346653,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346653,	//;Ch 12	2467
		0x100077, 0x200999, 0x346663,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346663	//;Ch 14	2484 
	},
	//table 10
	{
		0x100047, 0x200999, 0x34666B,   //;Null 
		0x100047, 0x200999, 0x34666B,	//;Ch 1		2412
		0x100047, 0x20099b, 0x34666B,   //;Ch 2		2417
		0x100067, 0x200998, 0x34666B,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34666B,	//;Ch 4		2427
		0x100067, 0x200999, 0x34664B,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34664B,	//;Ch 6		2437
		0x100057, 0x200998, 0x34664B,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34664B,	//;Ch 8		2447
		0x100057, 0x200999, 0x346673,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346673,	//;Ch 10	2457
		0x100077, 0x200998, 0x346673,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346673,	//;Ch 12	2467
		0x100077, 0x200999, 0x346653,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346653	//;Ch 14	2484 
	},
	//table 11
	{
		0x100047, 0x200999, 0x34665B,   //;Null 
		0x100047, 0x200999, 0x34665B,	//;Ch 1		2412
		0x100047, 0x20099b, 0x34665B,   //;Ch 2		2417
		0x100067, 0x200998, 0x34665B,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34665B,	//;Ch 4		2427
		0x100067, 0x200999, 0x34666B,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34666B,	//;Ch 6		2437
		0x100057, 0x200998, 0x34666B,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34666B,	//;Ch 8		2447
		0x100057, 0x200999, 0x34664B,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34664B,	//;Ch 10	2457
		0x100077, 0x200998, 0x34664B,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34664B,	//;Ch 12	2467
		0x100077, 0x200999, 0x346673,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346673	//;Ch 14	2484 
	},
	//table AUTOCAL
	{
		0x106847, 0x200999, 0x346662,   //;Null 
		0x106847, 0x200999, 0x346662,   //;Ch 1		2412
		0x106847, 0x20099b, 0x346662,   //;Ch 2		2417
		0x106867, 0x200998, 0x346662,   //;Ch 3		2422
		0x106867, 0x20099a, 0x346662,   //;Ch 4		2427
		0x106867, 0x200999, 0x346662,   //;Ch 5		2432
		0x106867, 0x20099b, 0x346662,   //;Ch 6		2437
		0x106857, 0x200998, 0x346662,   //;Ch 7		2442
		0x106857, 0x20099a, 0x346662,   //;Ch 8		2447
		0x106857, 0x200999, 0x346662,   //;Ch 9		2452
		0x106857, 0x20099b, 0x346662,   //;Ch 10	2457
		0x106877, 0x200998, 0x346662,   //;Ch 11	2462
		0x106877, 0x20099a, 0x346662,   //;Ch 12	2467
		0x106877, 0x200999, 0x346662,   //;Ch 13	2472
		0x10684f, 0x200ccc, 0x346662    //;Ch 14	2484 
	}
};  

 //OFDM
U32 UW2453RF_minicard[][45] = { 
	//talbe 1
	{
		0x100047, 0x200999, 0x34664D,   //;Null 
		0x100047, 0x200999, 0x34664D,   //;Ch 1		2412
		0x100047, 0x20099b, 0x34664D,   //;Ch 2		2417
		0x100067, 0x200998, 0x34604D,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34604D,	//;Ch 4		2427
		0x100067, 0x200999, 0x346675,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346675,	//;Ch 6		2437
		0x100057, 0x200998, 0x346475,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346075,	//;Ch 8		2447
		0x100057, 0x200999, 0x346655,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346655,	//;Ch 10	2457
		0x100077, 0x200998, 0x346665,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346665,	//;Ch 12	2467
		0x100077, 0x200999, 0x346665,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346665	//;Ch 14	2484 
	},
	//talbe 2
	{
		0x100047, 0x200999, 0x34666D,   //;Null 
		0x100047, 0x200999, 0x34666D,   //;Ch 1		2412
		0x100047, 0x20099b, 0x34666D,   //;Ch 2		2417
		0x100067, 0x200998, 0x34606D,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34606D,	//;Ch 4		2427
		0x100067, 0x200999, 0x34664D,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34664D,	//;Ch 6		2437
		0x100057, 0x200998, 0x34644D,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34604D,	//;Ch 8		2447
		0x100057, 0x200999, 0x346675,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346675,	//;Ch 10	2457
		0x100077, 0x200998, 0x346655,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346655,	//;Ch 12	2467
		0x100077, 0x200999, 0x346655,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346655	//;Ch 14	2484 
	},
	//talbe 3
	{
		0x100047, 0x200999, 0x34665D,   //;Null 
		0x100047, 0x200999, 0x34665D,   //;Ch 1		2412
		0x100047, 0x20099b, 0x34665D,   //;Ch 2		2417
		0x100067, 0x200998, 0x34605D,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34605D,	//;Ch 4		2427
		0x100067, 0x200999, 0x34666D,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34666D,	//;Ch 6		2437
		0x100057, 0x200998, 0x34646D,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34606D,	//;Ch 8		2447
		0x100057, 0x200999, 0x34664D,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34664D,	//;Ch 10	2457
		0x100077, 0x200998, 0x346675,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346675,	//;Ch 12	2467
		0x100077, 0x200999, 0x346675,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346675	//;Ch 14	2484 
	},
	//table 4
	{
		0x100047, 0x200999, 0x34667D,	//;Null 
		0x100047, 0x200999, 0x34667D,   //;Ch 1		2412
		0x100047, 0x20099b, 0x34667D,   //;Ch 2		2417
		0x100067, 0x200998, 0x34607D,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34607D,	//;Ch 4		2427
		0x100067, 0x200999, 0x34665D,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34665D,	//;Ch 6		2437
		0x100057, 0x200998, 0x34645D,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34605D,	//;Ch 8		2447
		0x100057, 0x200999, 0x34666D,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34666D,	//;Ch 10	2457
		0x100077, 0x200998, 0x34664D,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34664D,	//;Ch 12	2467
		0x100077, 0x200999, 0x34664D,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x34664D	//;Ch 14	2484 
	},
	//table 5
	{
		0x100047, 0x200999, 0x346643,   //;Null 
		0x100047, 0x200999, 0x346643,   //;Ch 1		2412
		0x100047, 0x20099b, 0x346643,   //;Ch 2		2417
		0x100067, 0x200998, 0x346043,	//;Ch 3		2422
		0x100067, 0x20099a, 0x346043,	//;Ch 4		2427
		0x100067, 0x200999, 0x34667D,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34667D,	//;Ch 6		2437
		0x100057, 0x200998, 0x34647D,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34607D,	//;Ch 8		2447
		0x100057, 0x200999, 0x34665D,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34665D,	//;Ch 10	2457
		0x100077, 0x200998, 0x34666D,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34666D,	//;Ch 12	2467
		0x100077, 0x200999, 0x34666D,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x34666D	//;Ch 14	2484 
	},
	//table 6
	{
		0x100047, 0x200999, 0x346663,   //;Null 
		0x100047, 0x200999, 0x346663,   //;Ch 1		2412
		0x100047, 0x20099b, 0x346663,   //;Ch 2		2417
		0x100067, 0x200998, 0x346063,	//;Ch 3		2422
		0x100067, 0x20099a, 0x346063,	//;Ch 4		2427
		0x100067, 0x200999, 0x346643,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346643,	//;Ch 6		2437
		0x100057, 0x200998, 0x346443,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346043,	//;Ch 8		2447
		0x100057, 0x200999, 0x34667D,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34667D,	//;Ch 10	2457
		0x100077, 0x200998, 0x34665D,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34665D,	//;Ch 12	2467
		0x100077, 0x200999, 0x34665D,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x34665D	//;Ch 14	2484 
	},
	//table 7
	{
		0x100047, 0x200999, 0x346653,   //;Null 
		0x100047, 0x200999, 0x346653,   //;Ch 1		2412
		0x100047, 0x20099b, 0x346653,   //;Ch 2		2417
		0x100067, 0x200998, 0x346053,	//;Ch 3		2422
		0x100067, 0x20099a, 0x346053,	//;Ch 4		2427
		0x100067, 0x200999, 0x346663,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346663,	//;Ch 6		2437
		0x100057, 0x200998, 0x346463,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346063,	//;Ch 8		2447
		0x100057, 0x200999, 0x346643,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346643,	//;Ch 10	2457
		0x100077, 0x200998, 0x34667D,	//;Ch 11	2462
		0x100077, 0x20099a, 0x34667D,	//;Ch 12	2467
		0x100077, 0x200999, 0x34667D,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x34667D	//;Ch 14	2484 
	},
	//table 8
	{
		0x100047, 0x200999, 0x346673,   //;Null 
		0x100047, 0x200999, 0x346673,   //;Ch 1		2412
		0x100047, 0x20099b, 0x346673,   //;Ch 2		2417
		0x100067, 0x200998, 0x346073,	//;Ch 3		2422
		0x100067, 0x20099a, 0x346073,	//;Ch 4		2427
		0x100067, 0x200999, 0x346653,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346653,	//;Ch 6		2437
		0x100057, 0x200998, 0x346453,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346053,	//;Ch 8		2447
		0x100057, 0x200999, 0x346663,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346663,	//;Ch 10	2457
		0x100077, 0x200998, 0x346643,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346643,	//;Ch 12	2467
		0x100077, 0x200999, 0x346643,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346643	//;Ch 14	2484 
	},
	//table 9
	{
		0x100047, 0x200999, 0x34664B,   //;Null 
		0x100047, 0x200999, 0x34664B,	//;Ch 1		2412
		0x100047, 0x20099b, 0x34664B,   //;Ch 2		2417
		0x100067, 0x200998, 0x34604B,	//;Ch 3	    2422
		0x100067, 0x20099a, 0x34604B,	//;Ch 4		2427
		0x100067, 0x200999, 0x346673,	//;Ch 5		2432
		0x100067, 0x20099b, 0x346673,	//;Ch 6		2437
		0x100057, 0x200998, 0x346473,	//;Ch 7		2442
		0x100057, 0x20099a, 0x346073,	//;Ch 8		2447
		0x100057, 0x200999, 0x346653,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346653,	//;Ch 10	2457
		0x100077, 0x200998, 0x346663,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346663,	//;Ch 12	2467
		0x100077, 0x200999, 0x346663,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346663	//;Ch 14	2484 
	},
	//table 10
	{
		0x100047, 0x200999, 0x34666B,   //;Null 
		0x100047, 0x200999, 0x34666B,	//;Ch 1		2412
		0x100047, 0x20099b, 0x34666B,   //;Ch 2		2417
		0x100067, 0x200998, 0x34606B,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34606B,	//;Ch 4		2427
		0x100067, 0x200999, 0x34664B,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34664B,	//;Ch 6		2437
		0x100057, 0x200998, 0x34644B,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34604B,	//;Ch 8		2447
		0x100057, 0x200999, 0x346673,	//;Ch 9		2452
		0x100057, 0x20099b, 0x346673,	//;Ch 10	2457
		0x100077, 0x200998, 0x346653,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346653,	//;Ch 12	2467
		0x100077, 0x200999, 0x346653,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346653	//;Ch 14	2484 
	},
	//table 11
	{
		0x100047, 0x200999, 0x34665B,   //;Null 
		0x100047, 0x200999, 0x34665B,	//;Ch 1		2412
		0x100047, 0x20099b, 0x34665B,   //;Ch 2		2417
		0x100067, 0x200998, 0x34605B,	//;Ch 3		2422
		0x100067, 0x20099a, 0x34605B,	//;Ch 4		2427
		0x100067, 0x200999, 0x34666B,	//;Ch 5		2432
		0x100067, 0x20099b, 0x34666B,	//;Ch 6		2437
		0x100057, 0x200998, 0x34646B,	//;Ch 7		2442
		0x100057, 0x20099a, 0x34606B,	//;Ch 8		2447
		0x100057, 0x200999, 0x34664B,	//;Ch 9		2452
		0x100057, 0x20099b, 0x34664B,	//;Ch 10	2457
		0x100077, 0x200998, 0x346673,	//;Ch 11	2462
		0x100077, 0x20099a, 0x346673,	//;Ch 12	2467
		0x100077, 0x200999, 0x346673,	//;Ch 13	2472
		0x10004f, 0x200ccc, 0x346673	//;Ch 14	2484 
	},
	//table AUTOCAL
	{
		0x106847, 0x200999, 0x346662,   //;Null 
		0x106847, 0x200999, 0x346662,   //;Ch 1		2412
		0x106847, 0x20099b, 0x346662,   //;Ch 2		2417
		0x106867, 0x200998, 0x346662,   //;Ch 3		2422
		0x106867, 0x20099a, 0x346662,   //;Ch 4		2427
		0x106867, 0x200999, 0x346662,   //;Ch 5		2432
		0x106867, 0x20099b, 0x346662,   //;Ch 6		2437
		0x106857, 0x200998, 0x346662,   //;Ch 7		2442
		0x106857, 0x20099a, 0x346662,   //;Ch 8		2447
		0x106857, 0x200999, 0x346662,   //;Ch 9		2452
		0x106857, 0x20099b, 0x346662,   //;Ch 10	2457
		0x106877, 0x200998, 0x346662,   //;Ch 11	2462
		0x106877, 0x20099a, 0x346662,   //;Ch 12	2467
		0x106877, 0x200999, 0x346662,   //;Ch 13	2472
		0x10684f, 0x200ccc, 0x346662    //;Ch 14	2484 
	}
};  

//CCK
U32 UW2453RF_CCK[][45] = { 
	//talbe 1
	{
		0x100047, 0x200999, 0x34664D,   //;Null 
		0x100047, 0x200999, 0x34664D,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x34664D,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x346675,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x346675,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x346675,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x346675,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x346655,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x346655,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x346655,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x346655,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x346665,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x346665,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x346665,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x346665    //;Ch 14	2484, 01110,+6
	},
	//talbe 2
	{
		0x100047, 0x200999, 0x34666D,   //;Null
		0x100047, 0x200999, 0x34666D,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x34666D,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x34664D,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x34664D,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x34664D,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x34664D,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x346675,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x346675,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x346675,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x346675,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x346655,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x346655,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x346655,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x346655    //;Ch 14	2484, 01110,+6
	},
	//talbe 3
	{
		0x100047, 0x200999, 0x34665D,   //;Null
		0x100047, 0x200999, 0x34665D,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x34665D,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x34666D,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x34666D,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x34666D,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x34666D,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x34664D,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x34664D,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x34664D,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x34664D,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x346675,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x346675,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x346675,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x346675    //;Ch 14	2484, 01110,+6
	},
	//table 4
	{
		0x100047, 0x200999, 0x34667D,	//;Null
		0x100047, 0x200999, 0x34667D,	//;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x34667D,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x34665D,   //;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x34665D,   //;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x34665D,   //;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x34665D,   //;Ch 6		2437, 
		0x100057, 0x200998, 0x34666D,   //;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x34666D,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x34666D,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x34666D,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x34664D,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x34664D,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x34664D,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x34664D    //;Ch 14	2484, 01110,+6
	},
	//table 5
	{
		0x100047, 0x200999, 0x346643,   //;Null
		0x100047, 0x200999, 0x346643,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x346643,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x34667D,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x34667D,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x34667D,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x34667D,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x34665D,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x34665D,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x34665D,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x34665D,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x34666D,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x34666D,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x34666D,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x34666D    //;Ch 14	2484, 01110,+6
	},
	//table 6
	{
		0x100047, 0x200999, 0x346663,   //;Null
		0x100047, 0x200999, 0x346663,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x346663,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x346643,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x346643,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x346643,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x346643,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x34667D,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x34667D,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x34667D,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x34667D,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x34665D,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x34665D,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x34665D,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x34665D    //;Ch 14	2484, 01110,+6
	},
	//table 7
	{
		0x100047, 0x200999, 0x346653,   //;Null
		0x100047, 0x200999, 0x346653,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x346653,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x346663,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x346663,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x346663,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x346663,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x346643,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x346643,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x346643,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x346643,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x34667D,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x34667D,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x34667D,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x34667D    //;Ch 14	2484, 01110,+6
	},
	//table 8
	{
		0x100047, 0x200999, 0x346673,   //;Null
		0x100047, 0x200999, 0x346673,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x346673,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x346653,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x346653,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x346653,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x346653,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x346663,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x346663,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x346663,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x346663,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x346643,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x346643,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x346643,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x346643    //;Ch 14	2484, 01110,+6
	},
	//table 9
	{
		0x100047, 0x200999, 0x34664B,   //;Null
		0x100047, 0x200999, 0x34664B,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x34664B,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x346673,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x346673,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x346673,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x346673,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x346653,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x346653,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x346653,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x346653,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x346663,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x346663,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x346663,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x346663    //;Ch 14	2484, 01110,+6
	},
	//table 10
	{
		0x100047, 0x200999, 0x34666B,   //;Null
		0x100047, 0x200999, 0x34666B,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x34666B,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x34664B,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x34664B,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x34664B,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x34664B,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x346673,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x346673,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x346673,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x346673,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x346653,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x346653,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x346653,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x346653    //;Ch 14	2484, 01110,+6
	},
	//table 11
	{
		0x100047, 0x200999, 0x34665B,   //;Null
		0x100047, 0x200999, 0x34665B,   //;Ch 1		2412, 10001,+6
		0x100047, 0x20099b, 0x34665B,   //;Ch 2		2417, 10001,+6
		0x100067, 0x200998, 0x34666B,	//;Ch 3		2422, offset -1(10000),+6
		0x100067, 0x20099a, 0x34666B,	//;Ch 4		2427, offset -1(10000),+6
		0x100067, 0x200999, 0x34666B,	//;Ch 5		2432, 10000,+6
		0x100067, 0x20099b, 0x34666B,	//;Ch 6		2437, 
		0x100057, 0x200998, 0x34664B,	//;Ch 7		2442, offset -1(01111),+6
		0x100057, 0x20099a, 0x34664B,	//;Ch 8		2447, offset -1(01111),+6
		0x100057, 0x200999, 0x34664B,	//;Ch 9		2452, 01111,+6
		0x100057, 0x20099b, 0x34664B,	//;Ch 10	2457, 01111,+6
		0x100077, 0x200998, 0x346673,	//;Ch 11	2462, offset -1(01110),+6
		0x100077, 0x20099a, 0x346673,	//;Ch 12	2467, offset -1(01110),+6
		0x100077, 0x200999, 0x346673,	//;Ch 13	2472, 01110,+6
		0x10004f, 0x200ccc, 0x346673    //;Ch 14	2484, 01110,+6
	},
	//table AUTOCAL
	{
		0x106847, 0x200999, 0x346762,   //;Null
		0x106847, 0x200999, 0x346762,   //;Ch 1	offset -1
		0x106847, 0x20099b, 0x346762,   //;Ch 2	offset -1
		0x106867, 0x200998, 0x346762,   //;Ch 3	offset -1
		0x106867, 0x20099a, 0x346762,   //;Ch 4	offset -1
		0x106867, 0x200999, 0x346762,   //;Ch 5	offset -1
		0x106867, 0x20099b, 0x346762,   //;Ch 6	offset -1
		0x106857, 0x200998, 0x346762,   //;Ch 7	offset -1
		0x106857, 0x20099a, 0x346762,   //;Ch 8	offset -1
		0x106857, 0x200999, 0x346762,   //;Ch 9	offset -1
		0x106857, 0x20099b, 0x346762,   //;Ch 10	offset -1
		0x106877, 0x200998, 0x346762,   //;Ch 11	offset -1
		0x106877, 0x20099a, 0x346762,   //;Ch 12	offset -1
		0x106877, 0x200999, 0x346762,   //;Ch 13	offset -1
		0x10684f, 0x200ccc, 0x346762     //;Ch 14	offset -1
	}
};
#endif
 //OFDM
#if ZDCONF_RF_UW2453_SUPPORT ==  1 || ZDCONF_RF_AR2124_SUPPORT == 1
U32 UW2453RF_HW[][45] = { 
	//table 1                                                    
	{                                                            
		0xe20008, 0x999004, 0xb2662c,   //;NULL                 
		0xe20008, 0x999004, 0xb2662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xb2662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xb2662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xb2662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xae662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xae662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xae662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xae662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xaa662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xaa662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xaa662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xaa662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xa6662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xa6662c    //;Ch 14		 2484
	},                                                           
	//table 2                                                    
	{                                                            
		0xe20008, 0x999004, 0xb6662c,   //;NULL                 
		0xe20008, 0x999004, 0xb6662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xb6662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xb6662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xb6662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xb2662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xb2662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xb2662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xb2662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xae662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xae662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xae662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xae662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xaa662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xaa662c    //;Ch 14		 2484
	},                                                           
	//table 3                                                    
	{                                                            
		0xe20008, 0x999004, 0xba662c,   //;NULL                 
		0xe20008, 0x999004, 0xba662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xba662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xba662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xba662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xb6662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xb6662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xb6662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xb6662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xb2662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xb2662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xb2662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xb2662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xae662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xae662c    //;Ch 14		 2484
	},                                                           
	//table 4                                                    
	{                                                            
		0xe20008, 0x999004, 0xbe662c,   //;NULL                 
		0xe20008, 0x999004, 0xbe662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xbe662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xbe662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xbe662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xba662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xba662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xba662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xba662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xb6662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xb6662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xb6662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xb6662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xb2662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xb2662c    //;Ch 14		 2484
	},                                                           
	//table 5                                                    
	{                                                            
		0xe20008, 0x999004, 0xc2662c,   //;NULL                 
		0xe20008, 0x999004, 0xc2662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xc2662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xc2662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xc2662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xbe662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xbe662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xbe662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xbe662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xba662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xba662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xba662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xba662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xb6662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xb6662c    //;Ch 14		 2484
	},                                                           
	//table 6                                                                                                                                                                                                                                          
	{                                                                                                                                                                                                                                                  
		0xe20008, 0x999004, 0xc6662c,   //;NULL                                                                                                                                                                                                       
		0xe20008, 0x999004, 0xc6662c,   //;Ch 1		 2412                                                                                                                                                                                      
		0xe20008, 0xd99004, 0xc6662c,   //;Ch 2		 2417                                                                                                                                                                                      
		0xe60008, 0x199004, 0xc6662c,   //;Ch 3		 2422                                                                                                                                                                                      
		0xe60008, 0x599004, 0xc6662c,   //;Ch 4		 2427                                                                                                                                                                                      
		0xe60008, 0x999004, 0xc2662c,   //;Ch 5		 2432                                                                                                                                                                                      
		0xe60008, 0xd99004, 0xc2662c,   //;Ch 6		 2437                                                                                                                                                                                      
		0xea0008, 0x199004, 0xc2662c,   //;Ch 7		 2442                                                                                                                                                                                      
		0xea0008, 0x599004, 0xc2662c,   //;Ch 8		 2447                                                                                                                                                                                      
		0xea0008, 0x999004, 0xbe662c,   //;Ch 9		 2452                                                                                                                                                                                      
		0xea0008, 0xd99004, 0xbe662c,   //;Ch 10		 2457                                                                                                                                                                                      
		0xee0008, 0x199004, 0xbe662c,   //;Ch 11		 2462                                                                                                                                                                                      
		0xee0008, 0x599004, 0xbe662c,   //;Ch 12		 2467                                                                                                                                                                                      
		0xee0008, 0x999004, 0xba662c,   //;Ch 13		 2472                                                                                                                                                                                      
		0xf20008, 0x333004, 0xba662c    //;Ch 14		 2484                                                                                                                                                                                      
	},                                                                                                                                                                                                                                                 
	//table 7                                                                                                                                                                                                                                          
	{                                                                                                                                                                                                                                                  
		0xe20008, 0x999004, 0xca662c,   //;NULL                                                                                                                                                                                                       
		0xe20008, 0x999004, 0xca662c,   //;Ch 1		 2412                                                                                                                                                                                      
		0xe20008, 0xd99004, 0xca662c,   //;Ch 2		 2417                                                                                                                                                                                      
		0xe60008, 0x199004, 0xca662c,   //;Ch 3		 2422                                                                                                                                                                                      
		0xe60008, 0x599004, 0xca662c,   //;Ch 4		 2427                                                                                                                                                                                      
		0xe60008, 0x999004, 0xc6662c,   //;Ch 5		 2432                                                                                                                                                                                      
		0xe60008, 0xd99004, 0xc6662c,   //;Ch 6		 2437                                                                                                                                                                                      
		0xea0008, 0x199004, 0xc6662c,   //;Ch 7		 2442                                                                                                                                                                                      
		0xea0008, 0x599004, 0xc6662c,   //;Ch 8		 2447                                                                                                                                                                                      
		0xea0008, 0x999004, 0xc2662c,   //;Ch 9		 2452                                                                                                                                                                                      
		0xea0008, 0xd99004, 0xc2662c,   //;Ch 10		 2457                                                                                                                                                                                      
		0xee0008, 0x199004, 0xc2662c,   //;Ch 11		 2462                                                                                                                                                                                      
		0xee0008, 0x599004, 0xc2662c,   //;Ch 12		 2467                                                                                                                                                                                      
		0xee0008, 0x999004, 0xbe662c,   //;Ch 13		 2472                                                                                                                                                                                      
		0xf20008, 0x333004, 0xbe662c    //;Ch 14		 2484                                                                                                                                                                                      
	},                                                                                                                                                                                                                                                 
	//table 8                                                                                                                                                                                                                                          
	{                                                                                                                                                                                                                                                  
		0xe20008, 0x999004, 0xce662c,   //;NULL                                                                                                                                                                                                       
		0xe20008, 0x999004, 0xce662c,   //;Ch 1		 2412                                                                                                                                                                                      
		0xe20008, 0xd99004, 0xce662c,   //;Ch 2		 2417                                                                                                                                                                                      
		0xe60008, 0x199004, 0xce662c,   //;Ch 3		 2422                                                                                                                                                                                      
		0xe60008, 0x599004, 0xce662c,   //;Ch 4		 2427                                                                                                                                                                                      
		0xe60008, 0x999004, 0xca662c,   //;Ch 5		 2432                                                                                                                                                                                      
		0xe60008, 0xd99004, 0xca662c,   //;Ch 6		 2437                                                                                                                                                                                      
		0xea0008, 0x199004, 0xca662c,   //;Ch 7		 2442                                                                                                                                                                                      
		0xea0008, 0x599004, 0xca662c,   //;Ch 8		 2447                                                                                                                                                                                      
		0xea0008, 0x999004, 0xc6662c,   //;Ch 9		 2452                                                                                                                                                                                      
		0xea0008, 0xd99004, 0xc6662c,   //;Ch 10		 2457                                                                                                                                                                                      
		0xee0008, 0x199004, 0xc6662c,   //;Ch 11		 2462                                                                                                                                                                                      
		0xee0008, 0x599004, 0xc6662c,   //;Ch 12		 2467                                                                                                                                                                                      
		0xee0008, 0x999004, 0xc2662c,   //;Ch 13		 2472                                                                                                                                                                                      
		0xf20008, 0x333004, 0xc2662c    //;Ch 14		 2484                                                                                                                                                                                      
	},                                                                                                                                                                                                                                                 
	//table 9                                                                                                                                                                                                                                          
	{                                                                                                                                                                                                                                                  
		0xe20008, 0x999004, 0xd2662c,   //;NULL                                                                                                                                                                                                       
		0xe20008, 0x999004, 0xd2662c,   //;Ch 1		 2412                                                                                                                                                                                      
		0xe20008, 0xd99004, 0xd2662c,   //;Ch 2		 2417                                                                                                                                                                                      
		0xe60008, 0x199004, 0xd2662c,   //;Ch 3		 2422                                                                                                                                                                                      
		0xe60008, 0x599004, 0xd2662c,   //;Ch 4		 2427                                                                                                                                                                                      
		0xe60008, 0x999004, 0xce662c,   //;Ch 5		 2432                                                                                                                                                                                      
		0xe60008, 0xd99004, 0xce662c,   //;Ch 6		 2437                                                                                                                                                                                      
		0xea0008, 0x199004, 0xce662c,   //;Ch 7		 2442                                                                                                                                                                                      
		0xea0008, 0x599004, 0xce662c,   //;Ch 8		 2447                                                                                                                                                                                      
		0xea0008, 0x999004, 0xca662c,   //;Ch 9		 2452                                                                                                                                                                                      
		0xea0008, 0xd99004, 0xca662c,   //;Ch 10		 2457                                                                                                                                                                                      
		0xee0008, 0x199004, 0xca662c,   //;Ch 11		 2462                                                                                                                                                                                      
		0xee0008, 0x599004, 0xca662c,   //;Ch 12		 2467                                                                                                                                                                                      
		0xee0008, 0x999004, 0xc6662c,   //;Ch 13		 2472                                                                                                                                                                                      
		0xf20008, 0x333004, 0xc6662c    //;Ch 14		 2484                                                                                                                                                                                      
	},                                                                                                                                                                                                                                                 
	//table 10                                                    
	{                                                             
		0xe20008, 0x999004, 0xd6662c,   //;NULL                  
		0xe20008, 0x999004, 0xd6662c,   //;Ch 1		 2412 
		0xe20008, 0xd99004, 0xd6662c,   //;Ch 2		 2417 
		0xe60008, 0x199004, 0xd6662c,   //;Ch 3		 2422 
		0xe60008, 0x599004, 0xd6662c,   //;Ch 4		 2427 
		0xe60008, 0x999004, 0xd2662c,   //;Ch 5		 2432 
		0xe60008, 0xd99004, 0xd2662c,   //;Ch 6		 2437 
		0xea0008, 0x199004, 0xd2662c,   //;Ch 7		 2442 
		0xea0008, 0x599004, 0xd2662c,   //;Ch 8		 2447 
		0xea0008, 0x999004, 0xce662c,   //;Ch 9		 2452 
		0xea0008, 0xd99004, 0xce662c,   //;Ch 10		 2457 
		0xee0008, 0x199004, 0xce662c,   //;Ch 11		 2462 
		0xee0008, 0x599004, 0xce662c,   //;Ch 12		 2467 
		0xee0008, 0x999004, 0xca662c,   //;Ch 13		 2472 
		0xf20008, 0x333004, 0xca662c    //;Ch 14		 2484 
	},                                                            
	//table 11                                                    
	{                                                             
		0xe20008, 0x999004, 0xda662c,   //;NULL                  
		0xe20008, 0x999004, 0xda662c,   //;Ch 1		 2412 
		0xe20008, 0xd99004, 0xda662c,   //;Ch 2		 2417 
		0xe60008, 0x199004, 0xda662c,   //;Ch 3		 2422 
		0xe60008, 0x599004, 0xda662c,   //;Ch 4		 2427 
		0xe60008, 0x999004, 0xd6662c,   //;Ch 5		 2432 
		0xe60008, 0xd99004, 0xd6662c,   //;Ch 6		 2437 
		0xea0008, 0x199004, 0xd6662c,   //;Ch 7		 2442 
		0xea0008, 0x599004, 0xd6662c,   //;Ch 8		 2447 
		0xea0008, 0x999004, 0xd2662c,   //;Ch 9		 2452 
		0xea0008, 0xd99004, 0xd2662c,   //;Ch 10		 2457 
		0xee0008, 0x199004, 0xd2662c,   //;Ch 11		 2462 
		0xee0008, 0x599004, 0xd2662c,   //;Ch 12		 2467 
		0xee0008, 0x999004, 0xce662c,   //;Ch 13		 2472 
		0xf20008, 0x333004, 0xce662c    //;Ch 14		 2484 
	},                                                            
	//table AUTOCAL                                                   
	{                                                             
		0xe21608, 0x999004, 0x46662c,   //;NULL                  
		0xe21608, 0x999004, 0x46662c,   //;Ch 1		 2412 
		0xe21608, 0xd99004, 0x46662c,   //;Ch 2		 2417 
		0xe61608, 0x199004, 0x46662c,   //;Ch 3		 2422 
		0xe61608, 0x599004, 0x46662c,   //;Ch 4		 2427 
		0xe61608, 0x999004, 0x46662c,   //;Ch 5		 2432 
		0xe61608, 0xd99004, 0x46662c,   //;Ch 6		 2437 
		0xea1608, 0x199004, 0x46662c,   //;Ch 7		 2442 
		0xea1608, 0x599004, 0x46662c,   //;Ch 8		 2447 
		0xea1608, 0x999004, 0x46662c,   //;Ch 9		 2452 
		0xea1608, 0xd99004, 0x46662c,   //;Ch 10		 2457 
		0xee1608, 0x199004, 0x46662c,   //;Ch 11		 2462 
		0xee1608, 0x599004, 0x46662c,   //;Ch 12		 2467 
		0xee1608, 0x999004, 0x46662c,   //;Ch 13		 2472 
		0xf21608, 0x333004, 0x46662c    //;Ch 14		 2484 
	}                                                                                                                                                                                                              
};  
#endif
#if ZDCONF_RF_UW2453_SUPPORT == 1
//CCK
U32 UW2453RF_CCK_HW[][45] = { 
	//table 1                                                    
	{                                                            
		0xe20008, 0x999004, 0xb2662c,   //;NULL                 
		0xe20008, 0x999004, 0xb2662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xb2662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xae662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xae662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xae662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xae662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xaa662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xaa662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xaa662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xaa662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xa6662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xa6662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xa6662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xa6662c    //;Ch 14		 2484
	},                                                           
	//table 2                                                    
	{                                                            
		0xe20008, 0x999004, 0xb6662c,   //;NULL                 
		0xe20008, 0x999004, 0xb6662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xb6662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xb2662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xb2662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xb2662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xb2662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xae662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xae662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xae662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xae662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xaa662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xaa662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xaa662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xaa662c    //;Ch 14		 2484
	},                                                           
	//table 3                                                    
	{                                                            
		0xe20008, 0x999004, 0xba662c,   //;NULL                 
		0xe20008, 0x999004, 0xba662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xba662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xb6662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xb6662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xb6662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xb6662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xb2662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xb2662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xb2662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xb2662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xae662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xae662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xae662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xae662c    //;Ch 14		 2484
	},                                                           
	//table 4                                                    
	{                                                            
		0xe20008, 0x999004, 0xbe662c,   //;NULL                 
		0xe20008, 0x999004, 0xbe662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xbe662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xba662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xba662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xba662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xba662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xb6662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xb6662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xb6662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xb6662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xb2662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xb2662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xb2662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xb2662c    //;Ch 14		 2484
	},                                                           
	//table 5                                                    
	{                                                            
		0xe20008, 0x999004, 0xc2662c,   //;NULL                 
		0xe20008, 0x999004, 0xc2662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xc2662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xbe662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xbe662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xbe662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xbe662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xba662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xba662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xba662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xba662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xb6662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xb6662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xb6662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xb6662c    //;Ch 14		 2484
	},                                                           
	//table 6                                                      
	{                                                              
		0xe20008, 0x999004, 0xc6662c,   //;NULL                   
		0xe20008, 0x999004, 0xc6662c,   //;Ch 1		 2412  
		0xe20008, 0xd99004, 0xc6662c,   //;Ch 2		 2417  
		0xe60008, 0x199004, 0xc2662c,   //;Ch 3		 2422  
		0xe60008, 0x599004, 0xc2662c,   //;Ch 4		 2427  
		0xe60008, 0x999004, 0xc2662c,   //;Ch 5		 2432  
		0xe60008, 0xd99004, 0xc2662c,   //;Ch 6		 2437  
		0xea0008, 0x199004, 0xbe662c,   //;Ch 7		 2442  
		0xea0008, 0x599004, 0xbe662c,   //;Ch 8		 2447  
		0xea0008, 0x999004, 0xbe662c,   //;Ch 9		 2452  
		0xea0008, 0xd99004, 0xbe662c,   //;Ch 10		 2457  
		0xee0008, 0x199004, 0xba662c,   //;Ch 11		 2462  
		0xee0008, 0x599004, 0xba662c,   //;Ch 12		 2467  
		0xee0008, 0x999004, 0xba662c,   //;Ch 13		 2472  
		0xf20008, 0x333004, 0xba662c    //;Ch 14		 2484  
	},                                                             
	//table 7                                                      
	{                                                              
		0xe20008, 0x999004, 0xca662c,   //;NULL                   
		0xe20008, 0x999004, 0xca662c,   //;Ch 1		 2412  
		0xe20008, 0xd99004, 0xca662c,   //;Ch 2		 2417  
		0xe60008, 0x199004, 0xc6662c,   //;Ch 3		 2422  
		0xe60008, 0x599004, 0xc6662c,   //;Ch 4		 2427  
		0xe60008, 0x999004, 0xc6662c,   //;Ch 5		 2432  
		0xe60008, 0xd99004, 0xc6662c,   //;Ch 6		 2437  
		0xea0008, 0x199004, 0xc2662c,   //;Ch 7		 2442  
		0xea0008, 0x599004, 0xc2662c,   //;Ch 8		 2447  
		0xea0008, 0x999004, 0xc2662c,   //;Ch 9		 2452  
		0xea0008, 0xd99004, 0xc2662c,   //;Ch 10		 2457  
		0xee0008, 0x199004, 0xbe662c,   //;Ch 11		 2462  
		0xee0008, 0x599004, 0xbe662c,   //;Ch 12		 2467  
		0xee0008, 0x999004, 0xbe662c,   //;Ch 13		 2472  
		0xf20008, 0x333004, 0xbe662c    //;Ch 14		 2484  
	},                                                             
	//table 8                                                      
	{                                                              
		0xe20008, 0x999004, 0xce662c,   //;NULL                   
		0xe20008, 0x999004, 0xce662c,   //;Ch 1		 2412  
		0xe20008, 0xd99004, 0xce662c,   //;Ch 2		 2417  
		0xe60008, 0x199004, 0xca662c,   //;Ch 3		 2422  
		0xe60008, 0x599004, 0xca662c,   //;Ch 4		 2427  
		0xe60008, 0x999004, 0xca662c,   //;Ch 5		 2432  
		0xe60008, 0xd99004, 0xca662c,   //;Ch 6		 2437  
		0xea0008, 0x199004, 0xc6662c,   //;Ch 7		 2442  
		0xea0008, 0x599004, 0xc6662c,   //;Ch 8		 2447  
		0xea0008, 0x999004, 0xc6662c,   //;Ch 9		 2452  
		0xea0008, 0xd99004, 0xc6662c,   //;Ch 10		 2457  
		0xee0008, 0x199004, 0xc2662c,   //;Ch 11		 2462  
		0xee0008, 0x599004, 0xc2662c,   //;Ch 12		 2467  
		0xee0008, 0x999004, 0xc2662c,   //;Ch 13		 2472  
		0xf20008, 0x333004, 0xc2662c    //;Ch 14		 2484  
	},                                                             
	//table 9                                                      
	{                                                              
		0xe20008, 0x999004, 0xd2662c,   //;NULL                   
		0xe20008, 0x999004, 0xd2662c,   //;Ch 1		 2412  
		0xe20008, 0xd99004, 0xd2662c,   //;Ch 2		 2417  
		0xe60008, 0x199004, 0xce662c,   //;Ch 3		 2422  
		0xe60008, 0x599004, 0xce662c,   //;Ch 4		 2427  
		0xe60008, 0x999004, 0xce662c,   //;Ch 5		 2432  
		0xe60008, 0xd99004, 0xce662c,   //;Ch 6		 2437  
		0xea0008, 0x199004, 0xca662c,   //;Ch 7		 2442  
		0xea0008, 0x599004, 0xca662c,   //;Ch 8		 2447  
		0xea0008, 0x999004, 0xca662c,   //;Ch 9		 2452  
		0xea0008, 0xd99004, 0xca662c,   //;Ch 10		 2457  
		0xee0008, 0x199004, 0xc6662c,   //;Ch 11		 2462  
		0xee0008, 0x599004, 0xc6662c,   //;Ch 12		 2467  
		0xee0008, 0x999004, 0xc6662c,   //;Ch 13		 2472  
		0xf20008, 0x333004, 0xc6662c    //;Ch 14		 2484  
	},                                                             
	//table 10                                                   
	{                                                            
		0xe20008, 0x999004, 0xd6662c,   //;NULL                 
		0xe20008, 0x999004, 0xd6662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xd6662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xd2662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xd2662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xd2662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xd2662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xce662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xce662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xce662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xce662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xca662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xca662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xca662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xca662c    //;Ch 14		 2484
	},                                                           
	//table 11                                                   
	{                                                            
		0xe20008, 0x999004, 0xda662c,   //;NULL                 
		0xe20008, 0x999004, 0xda662c,   //;Ch 1		 2412
		0xe20008, 0xd99004, 0xda662c,   //;Ch 2		 2417
		0xe60008, 0x199004, 0xd6662c,   //;Ch 3		 2422
		0xe60008, 0x599004, 0xd6662c,   //;Ch 4		 2427
		0xe60008, 0x999004, 0xd6662c,   //;Ch 5		 2432
		0xe60008, 0xd99004, 0xd6662c,   //;Ch 6		 2437
		0xea0008, 0x199004, 0xd2662c,   //;Ch 7		 2442
		0xea0008, 0x599004, 0xd2662c,   //;Ch 8		 2447
		0xea0008, 0x999004, 0xd2662c,   //;Ch 9		 2452
		0xea0008, 0xd99004, 0xd2662c,   //;Ch 10		 2457
		0xee0008, 0x199004, 0xce662c,   //;Ch 11		 2462
		0xee0008, 0x599004, 0xce662c,   //;Ch 12		 2467
		0xee0008, 0x999004, 0xce662c,   //;Ch 13		 2472
		0xf20008, 0x333004, 0xce662c    //;Ch 14		 2484
	},                                                           
	//Auto table                                                   
	{                                                            
		0xe21608, 0x999004, 0x46e62c,   //;NULL                 
		0xe21608, 0x999004, 0x46e62c,   //;Ch 1		 2412
		0xe21608, 0xd99004, 0x46e62c,   //;Ch 2		 2417
		0xe61608, 0x199004, 0x46e62c,   //;Ch 3		 2422
		0xe61608, 0x599004, 0x46e62c,   //;Ch 4		 2427
		0xe61608, 0x999004, 0x46e62c,   //;Ch 5		 2432
		0xe61608, 0xd99004, 0x46e62c,   //;Ch 6		 2437
		0xea1608, 0x199004, 0x46e62c,   //;Ch 7		 2442
		0xea1608, 0x599004, 0x46e62c,   //;Ch 8		 2447
		0xea1608, 0x999004, 0x46e62c,   //;Ch 9		 2452
		0xea1608, 0xd99004, 0x46e62c,   //;Ch 10		 2457
		0xee1608, 0x199004, 0x46e62c,   //;Ch 11		 2462
		0xee1608, 0x599004, 0x46e62c,   //;Ch 12		 2467
		0xee1608, 0x999004, 0x46e62c,   //;Ch 13		 2472
		0xf21608, 0x333004, 0x46e62c    //;Ch 14		 2484
	}                                                           
};
#endif







#if ZDCONF_RF_AL2232_SUPPORT == 1
U32 AL2232TB[] =
{
    0x03f790, 0x033331, 0x00000d,                 //;Null
    0x03f790, 0x033331, 0x00000d,                 //;Ch 1
    0x03f790, 0x0b3331, 0x00000d,                 //;Ch 2
    0x03e790, 0x033331, 0x00000d,                 //;Ch 3
    0x03e790, 0x0b3331, 0x00000d,                 //;Ch 4
    0x03f7a0, 0x033331, 0x00000d,                 //;Ch 5
    0x03f7a0, 0x0b3331, 0x00000d,                 //;Ch 6
    0x03e7a0, 0x033331, 0x00000d,                 //;Ch 7
    0x03e7a0, 0x0b3331, 0x00000d,                 //;Ch 8
    0x03f7b0, 0x033331, 0x00000d,                 //;Ch 9
    0x03f7b0, 0x0b3331, 0x00000d,                 //;Ch 10
    0x03E7b0, 0x033331, 0x00000d,                 //;Ch 11
    0x03e7b0, 0x0b3331, 0x00000d,                 //;Ch 12
    0x03f7c0, 0x033331, 0x00000d,                 //;Ch 13
    0x03e7c0, 0x066661, 0x00000d                  //;Ch 14
};
#endif
#if ZDCONF_RF_AL2230_SUPPORT == 1
U32 AL2230TB_1211[] = {
    0x03f790, 0x033331, 0x00000d,   //;Null 
    0x03f790, 0x033331, 0x00000d,   //;Ch 1
    0x03f790, 0x0b3331, 0x00000d,  //;Ch 2
    0x03e790, 0x033331, 0x00000d,  //;Ch 3
    0x03e790, 0x0b3331, 0x00000d,  //;Ch 4
    0x03f7a0, 0x033331, 0x00000d,  //;Ch 5
    0x03f7a0, 0x0b3331, 0x00000d,  //;Ch 6
    0x03e7a0, 0x033331, 0x00000d,  //;Ch 7
    0x03e7a0, 0x0b3331, 0x00000d,  //;Ch 8
    0x03f7b0, 0x033331, 0x00000d,  //;Ch 9
    0x03f7b0, 0x0b3331, 0x00000d,  //;Ch 10
    0x03E7b0, 0x033331, 0x00000d,  //;Ch 11
    0x03e7b0, 0x0b3331, 0x00000d,  //;Ch 12
    0x03f7c0, 0x033331, 0x00000d,  //;Ch 13
    0x03e7c0, 0x066661, 0x00000d   //;Ch 14
};

U32 AL2230TB[] = {
        0x09efc0, 0x8cccc0, 0xb00000,  //;Null 
        0x09efc0, 0x8cccc0, 0xb00000,  //;Ch 1
        0x09efc0, 0x8cccd0, 0xb00000,  //;Ch 2
        0x09e7c0, 0x8cccc0, 0xb00000,  //;Ch 3
        0x09e7c0, 0x8cccd0, 0xb00000,  //;Ch 4
        0x05efc0, 0x8cccc0, 0xb00000,  //;Ch 5
        0x05efc0, 0x8cccd0, 0xb00000,  //;Ch 6
        0x05e7c0, 0x8cccc0, 0xb00000,  //;Ch 7
        0x05e7c0, 0x8cccd0, 0xb00000,  //;Ch 8
        0x0defc0, 0x8cccc0, 0xb00000,  //;Ch 9
        0x0defc0, 0x8cccd0, 0xb00000,  //;Ch 10
        0x0de7c0, 0x8cccc0, 0xb00000,  //;Ch 11
        0x0de7c0, 0x8cccd0, 0xb00000,  //;Ch 12
        0x03efc0, 0x8cccc0, 0xb00000,  //;Ch 13
        0x03e7c0, 0x866660, 0xb00000   //;Ch 14
};
#endif
#if ZDCONF_RF_AL7230B_SUPPORT == 1
U32 AL7230BTB[] = {
		0x09ec04, 0x8cccc8,   //;Null 
		0x09ec00, 0x8cccc8,   //;Ch 1
		0x09ec00, 0x8cccd8,   //;Ch 2
		0x09ec00, 0x8cccc0,   //;Ch 3
		0x09ec00, 0x8cccd0,   //;Ch 4
		0x05ec00, 0x8cccc8,   //;Ch 5
		0x05ec00, 0x8cccd8,   //;Ch 6
		0x05ec00, 0x8cccc0,   //;Ch 7
		0x05ec00, 0x8cccd0,   //;Ch 8
		0x0dec00, 0x8cccc8,   //;Ch 9
		0x0dec00, 0x8cccd8,   //;Ch 10
		0x0dec00, 0x8cccc0,   //;Ch 11
		0x0dec00, 0x8cccd0,   //;Ch 12
		0x03ec00, 0x8cccc8,   //;Ch 13
		0x03ec00, 0x866660    //;Ch 14
};

U32 AL7230BTB_a[] = {
		0x06aff4, 0x855550, 0x47f8a2, 0x21ebfe,   //;Null
		0x02aff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;CH 8 , 5040MHz
		0x02aff0, 0x855550, 0x47f8a2, 0x21ebfe,   //;CH 12, 5060MHz
		0x0aaff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;CH 16, 5080MHz
		0x06aff0, 0x8aaaa0, 0x47f8a2, 0x21ebfe,   //;CH 34, 5170MHz
		0x06aff0, 0x855550, 0x47f8a2, 0x21ebfe,   //;Ch 36, 5180MHz
		0x0eaff0, 0x800008, 0x47f8a2, 0x21ebfe,   //;Ch 38, 5190MHz
		0x0eaff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 40, 5200MHz
		0x0eaff0, 0x855558, 0x47f8a2, 0x21ebfe,   //;Ch 42, 5210MHz
		0x0eaff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;Ch 44, 5220MHz, current support
		0x0eaff0, 0x8aaaa0, 0x47f8a2, 0x21ebfe,   //;Ch 46, 5230MHz
		0x0eaff0, 0x855550, 0x47f8a2, 0x21ebfe,   //;Ch 48, 5240MHz
		0x01aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 52, 5260MHz
		0x01aff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;Ch 56, 5280MHz, current support
		0x01aff0, 0x855550, 0x47f8a2, 0x21ebfe,   //;Ch 60, 5300MHz
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 64, 5320MHz
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 68, 5320MHz,dummy
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 72, 5320MHz,dummy
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 76, 5320MHz,dummy
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 80, 5320MHz,dummy
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 84, 5320MHz,dummy
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 88, 5320MHz,dummy
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 92, 5320MHz,dummy
		0x09aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 96, 5320MHz,dummy
		0x03aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 100, 5500MHz
		0x03aff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;Ch 104, 5520MHz
		0x03aff0, 0x855550, 0x47f8a2, 0x21ebfe,   //;Ch 108, 5540MHz
		0x0baff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 112, 5560MHz
		0x0baff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;Ch 116, 5580MHz
		0x0baff0, 0x855550, 0x47f8a2, 0x21ebfe,   //;Ch 120, 5600MHz
		0x07aff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 124, 5620MHz
		0x07aff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;Ch 128, 5640MHz
		0x07aff0, 0x855550, 0x47f8a2, 0x21ebfe,   //;Ch 132, 5660MHz
		0x0faff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 136, 5680MHz
		0x0faff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;Ch 140, 5700MHz
		0x0faff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;Ch 144, 5700MHz, dummy
		0x006ff0, 0x800018, 0x47f8a2, 0x21ebfe,   //;Ch 149, 5745MHz
		0x006ff0, 0x855540, 0x47f8a2, 0x21ebfe,   //;Ch 153, 5765MHz
		0x006ff0, 0x8aaab0, 0x47f8a2, 0x21ebfe,   //;Ch 157, 5785MHz
		0x086ff0, 0x800018, 0x47f8a2, 0x21ebfe,   //;Ch 161, 5805MHz
		0x086ff0, 0x855540, 0x47f8a2, 0x21ebfe,   //;Ch 165, 5825MHz
		0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe,   //;Ch 168, 5825MHz,dummy
		0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe,   //;Ch 172, 5825MHz,dummy
		0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe,   //;Ch 176, 5825MHz,dummy
		0x086ff0, 0x8d5540, 0x47f8a2, 0x21ebfe,   //;Ch 180, 5825MHz,dummy
		0x04aff0, 0x800000, 0x47f8a2, 0x21ebf6,   //;Ch 184, 4920MHz
		0x04aff0, 0x855550, 0x47f8a2, 0x21ebfe,   //;Ch 188, 4940MHz
		0x0caff0, 0x8aaaa8, 0x47f8a2, 0x21ebfe,   //;Ch 192, 4960MHz
		0x0caff0, 0x800000, 0x47f8a2, 0x21ebf6     //;Ch 196, 4980MHz
};
#endif
#if ZDCONF_RF_RFMD_SUPPORT == 1	

U32 RFMD2958t[] = {
    0x1422BD,   //Null 
    0x185D17,   //Null 
    0x181979,   //Ch 1
    0x1e6666,   //Ch 1
    0x181989,   //Ch 2
    0x1e6666,   //Ch 2
    0x181999,   //Ch 3
    0x1e6666,   //Ch 3
    0x1819a9,   //Ch 4
    0x1e6666,   //Ch 4
    0x1819b9,   //Ch 5
    0x1e6666,   //Ch 5
    0x1819c9,   //Ch 6
    0x1e6666,   //Ch 6
    0x1819d9,   //Ch 7
    0x1e6666,   //Ch 7
    0x1819e9,   //Ch 8
    0x1e6666,   //Ch 8
    0x1819f9,   //Ch 9
    0x1e6666,   //Ch 9
    0x181a09,   //Ch 10
    0x1e6666,   //Ch 10
    0x181a19,   //Ch 11
    0x1e6666,   //Ch 11
    0x181a29,   //Ch 12
    0x1e6666,   //Ch 12
    0x181a39,   //Ch 13
    0x1e6666,   //Ch 13
    0x181a60,   //Ch 14
    0x1c0000    //Ch 14
};
#endif

#if ZDCONF_RF_AR2124_SUPPORT == 1	
ZDTYPE_UWTxGain ZD_AR2124TxGain[] =
{
    //new gain table
	{0x12,0x73FFFF},
	{0x11,0x73FFDF},
	{0x10,0x72FFFF},
	{0x0F,0x72FFDF},
	{0x0E,0x737FFF},
	{0x0D,0x737FDF},
	{0x0C,0x727FFF},
	{0x0B,0x727FDF},
	{0x0A,0x727F9F},
	{0x09,0x70FFFF},
	{0x08,0x70FFDF},
	{0x07,0x70FF9F},
	{0x06,0x70FE9F},
	{0x05,0x717FFF},
	{0x04,0x717FDF},
	{0x03,0x717F9F},
	{0x02,0x717E9F},
	{0x01,0x707FFF},
	{0x00,0x707FDF},
};
#endif
#if ZDCONF_RF_UW2453_SUPPORT == 1
ZDTYPE_UWTxGain ZD_UW2453TxGain[] =
{
	{0x12,0x73FFFF},
	{0x11,0x73FB3F},
	{0x10,0x73FF33},
	{0x0F,0x73FF8B},
	{0x0E,0x737FBF},
	{0x0D,0x7361D7},
	{0x0C,0x71FFFF},
	{0x0B,0x71FF3F},
	{0x0A,0x71E6DB},
	{0x09,0x71F35B},
	{0x08,0x71F393},
	{0x07,0x71F693},
	{0x06,0x71F493},
	{0x05,0x71F093},
	{0x04,0x70EA93},
	{0x03,0x70F893},
	{0x02,0x70E093},
	{0x01,0x70FB13},
	{0x00,0x70E313},
};
#endif

#define SET_IF_SYNTHESIZER(macp, InputValue)       \
{                                                     \
	mFILL_WRITE_REGISTER( ZD_CR244, (U8) ((InputValue & 0xff0000)>>16));               \
	mFILL_WRITE_REGISTER( ZD_CR243, (U8) ((InputValue & 0xff00) >> 8));      \
	mFILL_WRITE_REGISTER( ZD_CR242, (U8) ((InputValue & 0xff)));   \
}             
#define mFILL_WRITE_REGISTER(addr0, value0) \
{                                           \
    WriteAddr[WriteIndex] = addr0;          \
    WriteData[WriteIndex ++] = value0;      \
}

/*
#ifndef HOST_IF_USB
void
HW_Set_IF_Synthesizer(zd_80211Obj_t *pObj, U32 InputValue)
{
	U32	S_bit_cnt;
	U32 tmpvalue;
	void *reg = pObj->reg;
	int i;

	
	S_bit_cnt = pObj->S_bit_cnt;

	InputValue = InputValue << (31 - S_bit_cnt);
	
#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )	
	pObj->SetReg(reg, ZD_LE2, 0);
	pObj->SetReg(reg, ZD_RF_IF_CLK, 0);
	
	while(S_bit_cnt){
		InputValue = InputValue << 1;
		if (InputValue & 0x80000000){
			pObj->SetReg(reg, ZD_RF_IF_DATA, 1);
		}
		else{
			pObj->SetReg(reg, ZD_RF_IF_DATA, 0);
		}
		pObj->SetReg(reg, ZD_RF_IF_CLK, 1);
		//pObj->DelayUs(50);
		pObj->SetReg(reg, ZD_RF_IF_CLK, 0);

		//pObj->DelayUs(50);
		S_bit_cnt --;
	}
	
	pObj->SetReg(reg, ZD_LE2, 1);
	
	if (pObj->S_bit_cnt == 20){			//Is it Intersil's chipset
		pObj->SetReg(reg, ZD_LE2, 0);
	}
	return;
#else
	LockPhyReg(pObj);
	tmpvalue = pObj->GetReg(reg, ZD_CR203);
	tmpvalue &= ~BIT_1;
	pObj->SetReg(reg, ZD_CR203, tmpvalue);

	tmpvalue = pObj->GetReg(reg, ZD_CR240);
	tmpvalue = 0x80;
	if (tmpvalue & BIT_7){		// Configure RF by Software
		tmpvalue = pObj->GetReg(reg, ZD_CR203);
		tmpvalue &= ~BIT_2;
		pObj->SetReg(reg, ZD_CR203, tmpvalue);


		while(S_bit_cnt){
			InputValue = InputValue << 1;
			if (InputValue & 0x80000000){
				tmpvalue = pObj->GetReg(reg, ZD_CR203);
				tmpvalue |= BIT_3;
				pObj->SetReg(reg, ZD_CR203, tmpvalue);
			}
			else{
				tmpvalue = pObj->GetReg(reg, ZD_CR203);
				tmpvalue &= ~BIT_3;
				pObj->SetReg(reg, ZD_CR203, tmpvalue);
			}

			tmpvalue = pObj->GetReg(reg, ZD_CR203);
			tmpvalue |= BIT_2;
			pObj->SetReg(reg, ZD_CR203, tmpvalue);

			tmpvalue = pObj->GetReg(reg, ZD_CR203);

			tmpvalue &= ~BIT_2;
			pObj->SetReg(reg, ZD_CR203, tmpvalue);
			S_bit_cnt --;
		}
	}
	else{		// Configure RF by Hardware
		// Make Bit-reverse to meet hardware requirement.
		tmpvalue = 0;
		for (i=0; i<S_bit_cnt; i++){
			InputValue = InputValue << 1;
			if (InputValue & 0x80000000){
				tmpvalue |= (0x1 << i);
			}
		}
		InputValue = tmpvalue;

		// Setup Command-Length
		// wait until command-queue is available
		tmpvalue = pObj->GetReg(reg, ZD_CR241);
		while(tmpvalue & BIT_0){
			pObj->DelayUs(1);
			FPRINT("Command-Queue busy...");
		}

		// write command (from high-byte to low-byte)
		pObj->SetReg(reg, ZD_CR245, InputValue >> 24);
		pObj->SetReg(reg, ZD_CR244, InputValue >> 16);
		pObj->SetReg(reg, ZD_CR243, InputValue >> 8);
		pObj->SetReg(reg, ZD_CR242, InputValue);
	}
	

	tmpvalue = pObj->GetReg(reg, ZD_CR203);
	tmpvalue |= BIT_1;
	pObj->SetReg(reg, ZD_CR203, tmpvalue);

	if (pObj->S_bit_cnt == 20){			//Is it Intersil's chipset
		tmpvalue = pObj->GetReg(reg, ZD_CR203);
		tmpvalue &= ~BIT_1;
		pObj->SetReg(reg, ZD_CR203, tmpvalue);
	}
	
	UnLockPhyReg(pObj);
	return;	
#endif	
}
#endif
*/

void
LockPhyReg(zd_80211Obj_t *pObj)
{
#ifndef fQuickPhySet

	void *reg = pObj->reg;
	U32	tmpvalue;
#if 1
	tmpvalue = pObj->GetReg(reg, ZD_CtlReg1);
	tmpvalue &= ~0x80;
	pObj->SetReg(reg, ZD_CtlReg1, tmpvalue);
#else
	tmpvalue = 0x20;
	pObj->SetReg(reg, ZD_CtlReg1, tmpvalue);
#endif
#endif	
}


void
UnLockPhyReg(zd_80211Obj_t *pObj)
{
#ifndef fQuickPhySet	
	void *reg = pObj->reg;
	U32	tmpvalue;

#if 1
	tmpvalue = pObj->GetReg(reg, ZD_CtlReg1);
	tmpvalue |= 0x80;
	pObj->SetReg(reg, ZD_CtlReg1, tmpvalue);
#else
	tmpvalue = 0xA0;
	pObj->SetReg(reg, ZD_CtlReg1, tmpvalue);
#endif
#endif	
}
#if ZDCONF_RF_UW2453_SUPPORT == 1
void PHY_UW_IF_Synthesizer(zd_80211Obj_t *pObj, U16 ChannelNo, U8 Mode)
{
    if (Mode == 0)
    { // OFDM
        HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3+2]);
    }
    else if (Mode == 1) 
    { // CCK
        HW_Set_IF_Synthesizer(pObj, UW2453RF_CCK[pObj->UW2453RFTableIndex][ChannelNo*3+2]);
    }
}
#endif

#if ZDCONF_RF_UW2453_SUPPORT == 1 || ZDCONF_RF_AR2124_SUPPORT == 1
void PHY_UWTxPower(zd_80211Obj_t *pObj, U8 TxLevel)
{
    PZDTYPE_UWTxGain pTxGain;
    int     i;
    
    if (pObj->rfMode == UW2453_RF)
    {
        pTxGain = &ZD_UW2453TxGain[0];
        //printk(KERN_DEBUG "Use UW2453 Tx Gain tbl\n");
    }
#if ZDCONF_RF_AR2124_SUPPORT == 1
    else 
    {
        pTxGain = &ZD_AR2124TxGain[0];
        //printk(KERN_DEBUG "Use AR2124 Tx Gain tbl\n");
    }
#endif
    for(i=0;i<19;i++)
    {
        if(TxLevel == pTxGain[i].UWTxGainLevel)
            break;
    }
    if(i<19)
    {
        HW_Set_IF_Synthesizer(pObj, pTxGain[i].UWTxGainValue);
        pObj->UWCurrentTxLevel = pTxGain[i].UWTxGainLevel;
    }
    //printk(KERN_DEBUG "(i=%d)Tx GainLevel: 0x%X GainVAlue : 0x%X\n", i, pTxGain[i].UWTxGainLevel, pTxGain[i].UWTxGainValue);
}
#endif

/*
void
HW_Set_Maxim_New_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
	void *reg = pObj->reg;
	U32 tmpvalue;
	
	LockPhyReg(pObj);
	
#ifdef HOST_IF_USB
	pObj->SetReg(reg, ZD_CR23, 0x40);
	pObj->SetReg(reg, ZD_CR15, 0x20);
	pObj->SetReg(reg, ZD_CR28, 0x3e);
	pObj->SetReg(reg, ZD_CR29, 0x00);
	pObj->SetReg(reg, ZD_CR26, 0x11);
	pObj->SetReg(reg, ZD_CR44, 0x33);
	pObj->SetReg(reg, ZD_CR106, 0x2a);
	pObj->SetReg(reg, ZD_CR107, 0x1a);

	pObj->SetReg(reg, ZD_CR109, 0x2b);
	pObj->SetReg(reg, ZD_CR110, 0x2b);
	pObj->SetReg(reg, ZD_CR111, 0x2b);
	pObj->SetReg(reg, ZD_CR112, 0x2b);
	pObj->SetReg(reg, ZD_CR10, 0x89);
	pObj->SetReg(reg, ZD_CR17, 0x20);
	pObj->SetReg(reg, ZD_CR26, 0x93);
	pObj->SetReg(reg, ZD_CR34, 0x30);
	pObj->SetReg(reg, ZD_CR35, 0x40);
	pObj->SetReg(reg, ZD_CR41, 0x24);
	pObj->SetReg(reg, ZD_CR44, 0x32);
	pObj->SetReg(reg, ZD_CR46, 0x90);
	pObj->SetReg(reg, ZD_CR89, 0x18);
	pObj->SetReg(reg, ZD_CR92, 0x0a);

	pObj->SetReg(reg, ZD_CR101, 0x13);
	pObj->SetReg(reg, ZD_CR102, 0x27);
	pObj->SetReg(reg, ZD_CR106, 0x20);
	pObj->SetReg(reg, ZD_CR107, 0x24);
	pObj->SetReg(reg, ZD_CR109, 0x09);
	pObj->SetReg(reg, ZD_CR110, 0x13);
	pObj->SetReg(reg, ZD_CR111, 0x13);
	pObj->SetReg(reg, ZD_CR112, 0x13);
	pObj->SetReg(reg, ZD_CR113, 0x27);
	pObj->SetReg(reg, ZD_CR114, 0x27);
	pObj->SetReg(reg, ZD_CR115, 0x24);
	pObj->SetReg(reg, ZD_CR116, 0x24);
	pObj->SetReg(reg, ZD_CR117, 0xf4);
	pObj->SetReg(reg, ZD_CR118, 0xfa);
	pObj->SetReg(reg, ZD_CR120, 0x4f);
	pObj->SetReg(reg, ZD_CR121, 0x77);
	pObj->SetReg(reg, ZD_CR122, 0xfe);
#else	
	pObj->SetReg(reg, ZD_CR23, 0x40);
	pObj->SetReg(reg, ZD_CR15, 0x20);
	pObj->SetReg(reg, ZD_CR28, 0x3e);
	pObj->SetReg(reg, ZD_CR29, 0x00);
	pObj->SetReg(reg, ZD_CR26, 0x11);
	pObj->SetReg(reg, ZD_CR44, 0x34); //4112
	pObj->SetReg(reg, ZD_CR106, 0x2a);
	pObj->SetReg(reg, ZD_CR107, 0x1a);
	pObj->SetReg(reg, ZD_CR109, 0x2b);
	pObj->SetReg(reg, ZD_CR110, 0x2b);
	pObj->SetReg(reg, ZD_CR111, 0x2b);
	pObj->SetReg(reg, ZD_CR112, 0x2b);
	
#if (defined(GCCK) && defined(OFDM))
	pObj->SetReg(reg, ZD_CR10, 0x89);
	pObj->SetReg(reg, ZD_CR17, 0x20);
	pObj->SetReg(reg, ZD_CR26, 0x93);
	pObj->SetReg(reg, ZD_CR34, 0x30);
	pObj->SetReg(reg, ZD_CR35, 0x40);

	pObj->SetReg(reg, ZD_CR41, 0x24);
	pObj->SetReg(reg, ZD_CR44, 0x32);
	pObj->SetReg(reg, ZD_CR46, 0x90);
	pObj->SetReg(reg, ZD_CR89, 0x18);
	pObj->SetReg(reg, ZD_CR92, 0x0a);
	pObj->SetReg(reg, ZD_CR101, 0x13);
	pObj->SetReg(reg, ZD_CR102, 0x27);
	pObj->SetReg(reg, ZD_CR106, 0x20);
	pObj->SetReg(reg, ZD_CR107, 0x24);
	//pObj->SetReg(reg, ZD_CR109, 0x09);
	//pObj->SetReg(reg, ZD_CR110, 0x13);
	//pObj->SetReg(reg, ZD_CR111, 0x13);




	pObj->SetReg(reg, ZD_CR109, 0x13); //4326	
	pObj->SetReg(reg, ZD_CR110, 0x27); //4326
	pObj->SetReg(reg, ZD_CR111, 0x27); //4326
	pObj->SetReg(reg, ZD_CR112, 0x13);
	pObj->SetReg(reg, ZD_CR113, 0x27);
	pObj->SetReg(reg, ZD_CR114, 0x27);
	pObj->SetReg(reg, ZD_CR115, 0x24);
	pObj->SetReg(reg, ZD_CR116, 0x24);
	pObj->SetReg(reg, ZD_CR117, 0xf4);
	//pObj->SetReg(reg, ZD_CR118, 0xfa);
	pObj->SetReg(reg, ZD_CR118, 0x00); //4326
	pObj->SetReg(reg, ZD_CR120, 0x4f);
	//pObj->SetReg(reg, ZD_CR121, 0x77); //3n12
	//pObj->SetReg(reg, ZD_CR121, 0x13); //3d24
	pObj->SetReg(reg, ZD_CR121, 0x06); //4326
	pObj->SetReg(reg, ZD_CR122, 0xfe);
	pObj->SetReg(reg, ZD_CR150, 0x0d); //4407
	
#elif (defined(ECCK_60_5))	
	pObj->SetReg(reg, ZD_CR26, 0x91);
	pObj->SetReg(reg, ZD_CR47, 0x1E);
	pObj->SetReg(reg, ZD_CR106, 0x44);
	pObj->SetReg(reg, ZD_CR107, 0x00);
	pObj->SetReg(reg, ZD_CR14, 0x80);
	pObj->SetReg(reg, ZD_CR10, 0x89);
	pObj->SetReg(reg, ZD_CR11, 0x00);
	pObj->SetReg(reg, ZD_CR24, 0x0e);
	pObj->SetReg(reg, ZD_CR41, 0x24);
	pObj->SetReg(reg, ZD_CR159, 0x93);
	pObj->SetReg(reg, ZD_CR160, 0xfc);
	pObj->SetReg(reg, ZD_CR161, 0x1e);
	pObj->SetReg(reg, ZD_CR162, 0x24);
#endif
#endif
	
	pObj->CR122Flag = 2;
	pObj->CR31Flag = 2;
	
	//UnLockPhyReg(pObj);

#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
	pObj->SetReg(reg, ZD_PE1_PE2, 0x02);
#else	
	//LockPhyReg(pObj);
	tmpvalue = pObj->GetReg(reg, ZD_CR203);
	tmpvalue &= ~BIT_4;
	pObj->SetReg(reg, ZD_CR203, tmpvalue);
	//UnLockPhyReg(pObj);
#endif

	HW_Set_IF_Synthesizer(pObj, M2827BF[ChannelNo]);
	HW_Set_IF_Synthesizer(pObj, M2827BN[ChannelNo]);
	HW_Set_IF_Synthesizer(pObj, 0x00400);
	HW_Set_IF_Synthesizer(pObj, 0x00ca1);
	HW_Set_IF_Synthesizer(pObj, 0x10072);
	HW_Set_IF_Synthesizer(pObj, 0x18645);
	HW_Set_IF_Synthesizer(pObj, 0x04006);
	HW_Set_IF_Synthesizer(pObj, 0x000a7);
	HW_Set_IF_Synthesizer(pObj, 0x08258);
	HW_Set_IF_Synthesizer(pObj, 0x03fc9);
	HW_Set_IF_Synthesizer(pObj, 0x0040a);
	HW_Set_IF_Synthesizer(pObj, 0x0000b);
	HW_Set_IF_Synthesizer(pObj, 0x0026c);
#if	defined(ECCK_60_5)
	HW_Set_IF_Synthesizer(pObj, 0x04258);
#endif	
	
#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
	pObj->SetReg(reg, ZD_PE1_PE2, 0x03);
#else	
	//LockPhyReg(pObj);
	tmpvalue = pObj->GetReg(reg, ZD_CR203);
	tmpvalue |= BIT_4;

	pObj->SetReg(reg, ZD_CR203, tmpvalue);;
	//UnLockPhyReg(pObj);
#endif

    UnLockPhyReg(pObj);
}



void
HW_Set_Maxim_New_Chips2(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
	void *reg = pObj->reg;
	U32	tmpvalue;

	// Get Phy-Config permission
	LockPhyReg(pObj);

#ifdef HOST_IF_USB	
	pObj->SetReg(reg, ZD_CR23, 0x40);
	pObj->SetReg(reg, ZD_CR15, 0x20);
	pObj->SetReg(reg, ZD_CR28, 0x3e);
	pObj->SetReg(reg, ZD_CR29, 0x00);
	pObj->SetReg(reg, ZD_CR26, 0x11);
	pObj->SetReg(reg, ZD_CR44, 0x33);
	pObj->SetReg(reg, ZD_CR106, 0x2a);
	pObj->SetReg(reg, ZD_CR107, 0x1a);
	pObj->SetReg(reg, ZD_CR109, 0x2b);
	pObj->SetReg(reg, ZD_CR110, 0x2b);
	pObj->SetReg(reg, ZD_CR111, 0x2b);
	pObj->SetReg(reg, ZD_CR112, 0x2b);
	pObj->SetReg(reg, ZD_CR10, 0x89);
	pObj->SetReg(reg, ZD_CR17, 0x20);
	pObj->SetReg(reg, ZD_CR26, 0x93);
	pObj->SetReg(reg, ZD_CR34, 0x30);
	pObj->SetReg(reg, ZD_CR35, 0x40);
	pObj->SetReg(reg, ZD_CR41, 0x24);
	pObj->SetReg(reg, ZD_CR44, 0x32);
	pObj->SetReg(reg, ZD_CR46, 0x90);
	pObj->SetReg(reg, ZD_CR89, 0x18);
	pObj->SetReg(reg, ZD_CR92, 0x0a);
	pObj->SetReg(reg, ZD_CR101, 0x13);
	pObj->SetReg(reg, ZD_CR102, 0x27);
	pObj->SetReg(reg, ZD_CR106, 0x20);
	pObj->SetReg(reg, ZD_CR107, 0x24);
	pObj->SetReg(reg, ZD_CR109, 0x09);
	pObj->SetReg(reg, ZD_CR110, 0x13);
	pObj->SetReg(reg, ZD_CR111, 0x13);
	pObj->SetReg(reg, ZD_CR112, 0x13);
	pObj->SetReg(reg, ZD_CR113, 0x27);
	pObj->SetReg(reg, ZD_CR114, 0x27);
	pObj->SetReg(reg, ZD_CR115, 0x24);
	pObj->SetReg(reg, ZD_CR116, 0x24);

	pObj->SetReg(reg, ZD_CR117, 0xf4);
	pObj->SetReg(reg, ZD_CR118, 0xfa);
	pObj->SetReg(reg, ZD_CR120, 0x4f);
	
	pObj->SetReg(reg, ZD_CR121, 0x77);
	

	pObj->SetReg(reg, ZD_CR122, 0xfe);
	
#else	
	pObj->SetReg(reg, ZD_CR23, 0x40);
	pObj->SetReg(reg, ZD_CR15, 0x20);
	pObj->SetReg(reg, ZD_CR28, 0x3e);
	pObj->SetReg(reg, ZD_CR29, 0x00);
	pObj->SetReg(reg, ZD_CR26, 0x11);
	pObj->SetReg(reg, ZD_CR44, 0x33);
	pObj->SetReg(reg, ZD_CR106, 0x2a);
	pObj->SetReg(reg, ZD_CR107, 0x1a);
	pObj->SetReg(reg, ZD_CR109, 0x2b);
	pObj->SetReg(reg, ZD_CR110, 0x2b);
	pObj->SetReg(reg, ZD_CR111, 0x2b);
	pObj->SetReg(reg, ZD_CR112, 0x2b);
	
#if (defined(GCCK) && defined(OFDM))
	pObj->SetReg(reg, ZD_CR10, 0x89);
	pObj->SetReg(reg, ZD_CR17, 0x20);
	pObj->SetReg(reg, ZD_CR26, 0x93);
	pObj->SetReg(reg, ZD_CR34, 0x30);
	pObj->SetReg(reg, ZD_CR35, 0x40);
	pObj->SetReg(reg, ZD_CR41, 0x24);
	pObj->SetReg(reg, ZD_CR44, 0x32);

	pObj->SetReg(reg, ZD_CR46, 0x90);
	pObj->SetReg(reg, ZD_CR79, 0x58); //for Atheros compability 4415
	pObj->SetReg(reg, ZD_CR80, 0x30); //for Atheros compability
	pObj->SetReg(reg, ZD_CR81, 0x30); //for Atheros compability
	pObj->SetReg(reg, ZD_CR89, 0x18);







	pObj->SetReg(reg, ZD_CR92, 0x0a);
	pObj->SetReg(reg, ZD_CR101, 0x13);
	pObj->SetReg(reg, ZD_CR102, 0x27);
	pObj->SetReg(reg, ZD_CR106, 0x20);
	pObj->SetReg(reg, ZD_CR107, 0x24);
	pObj->SetReg(reg, ZD_CR109, 0x09);
	pObj->SetReg(reg, ZD_CR110, 0x13);
	pObj->SetReg(reg, ZD_CR111, 0x13);
	pObj->SetReg(reg, ZD_CR112, 0x13);
	pObj->SetReg(reg, ZD_CR113, 0x27);
	pObj->SetReg(reg, ZD_CR114, 0x27);
	pObj->SetReg(reg, ZD_CR115, 0x24);
	pObj->SetReg(reg, ZD_CR116, 0x24);
	pObj->SetReg(reg, ZD_CR117, 0xf4);
	//pObj->SetReg(reg, ZD_CR118, 0xfa);
	pObj->SetReg(reg, ZD_CR118, 0x00); //4326
	pObj->SetReg(reg, ZD_CR120, 0x4f);
	//pObj->SetReg(reg, ZD_CR121, 0x77); //3n12
	//pObj->SetReg(reg, ZD_CR121, 0x13); //3d24
	pObj->SetReg(reg, ZD_CR121, 0x06); //4326
	pObj->SetReg(reg, ZD_CR122, 0xfe);
#elif (defined(ECCK_60_5))

	pObj->SetReg(reg, ZD_CR47, 0x1E);
	pObj->SetReg(reg, ZD_CR106, 0x04);
	pObj->SetReg(reg, ZD_CR107, 0x00);
	pObj->SetReg(reg, ZD_CR14, 0x80);
	pObj->SetReg(reg, ZD_CR10, 0x89);

	pObj->SetReg(reg, ZD_CR11, 0x00);
	pObj->SetReg(reg, ZD_CR161, 0x28);
	pObj->SetReg(reg, ZD_CR162, 0x26);

	pObj->SetReg(reg, ZD_CR24, 0x0e);
	pObj->SetReg(reg, ZD_CR41, 0x24);
	pObj->SetReg(reg, ZD_CR159, 0x93);
	pObj->SetReg(reg, ZD_CR160, 0xfc);
	pObj->SetReg(reg, ZD_CR161, 0x20);
	pObj->SetReg(reg, ZD_CR162, 0x26);
#endif
#endif

	pObj->CR122Flag = 2;
	pObj->CR31Flag = 2;
	
	//UnLockPhyReg(pObj);

#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
	pObj->SetReg(reg, ZD_PE1_PE2, 2);
#else
	//LockPhyReg(pObj);
	tmpvalue = pObj->GetReg(reg, ZD_CR203);
	tmpvalue &= ~BIT_4;
	pObj->SetReg(reg, ZD_CR203, tmpvalue);
	//UnLockPhyReg(pObj);
#endif

	HW_Set_IF_Synthesizer(pObj, M2827BF2[ChannelNo]);
	HW_Set_IF_Synthesizer(pObj, M2827BN2[ChannelNo]);
	HW_Set_IF_Synthesizer(pObj, 0x00400);
	HW_Set_IF_Synthesizer(pObj, 0x00ca1);
	HW_Set_IF_Synthesizer(pObj, 0x10072);
	HW_Set_IF_Synthesizer(pObj, 0x18645);
	HW_Set_IF_Synthesizer(pObj, 0x04006);
	HW_Set_IF_Synthesizer(pObj, 0x000a7);
	HW_Set_IF_Synthesizer(pObj, 0x08258);

	HW_Set_IF_Synthesizer(pObj, 0x03fc9);
	HW_Set_IF_Synthesizer(pObj, 0x0040a);
	HW_Set_IF_Synthesizer(pObj, 0x0000b);
	HW_Set_IF_Synthesizer(pObj, 0x0026c);
#if	defined(ECCK_60_5)
	HW_Set_IF_Synthesizer(pObj, 0x04258);
#endif

#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )

	pObj->SetReg(reg, ZD_PE1_PE2, 3);

#else
	//LockPhyReg(pObj);
	tmpvalue = pObj->GetReg(reg, ZD_CR203);
	tmpvalue |= BIT_4;
	pObj->SetReg(reg, ZD_CR203, tmpvalue);
	//UnLockPhyReg(pObj);
#endif
    UnLockPhyReg(pObj);
}


void
HW_Set_GCT_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
	void *reg = pObj->reg;
	
	if (!InitChOnly){
		LockPhyReg(pObj);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		pObj->SetReg(reg, ZD_CR15, 0xdc);
		pObj->SetReg(reg, ZD_CR113, 0xc0); //3910
		pObj->SetReg(reg, ZD_CR20, 0x0c);
		pObj->SetReg(reg, ZD_CR17, 0x65);
		pObj->SetReg(reg, ZD_CR34, 0x04);
		pObj->SetReg(reg, ZD_CR35, 0x35);
		pObj->SetReg(reg, ZD_CR24, 0x20);
		pObj->SetReg(reg, ZD_CR9, 0xe0);
		pObj->SetReg(reg, ZD_CR127, 0x02);
		pObj->SetReg(reg, ZD_CR10, 0x91);
		pObj->SetReg(reg, ZD_CR23, 0x7f);
		pObj->SetReg(reg, ZD_CR27, 0x10);
		pObj->SetReg(reg, ZD_CR28, 0x7a);
		pObj->SetReg(reg, ZD_CR79, 0xb5);
		pObj->SetReg(reg, ZD_CR64, 0x80);
		//++ Enable D.C cancellation (CR33 Bit_5) to avoid
		//	 CCA always high.
		pObj->SetReg(reg, ZD_CR33, 0x28);
		//--                  

		pObj->SetReg(reg, ZD_CR38, 0x30);

		UnLockPhyReg(pObj);
	
		HW_Set_IF_Synthesizer(pObj, 0x1F0000);
		HW_Set_IF_Synthesizer(pObj, 0x1F0000);
		HW_Set_IF_Synthesizer(pObj, 0x1F0200);
		HW_Set_IF_Synthesizer(pObj, 0x1F0600);
		HW_Set_IF_Synthesizer(pObj, 0x1F8600);
		HW_Set_IF_Synthesizer(pObj, 0x1F8600);
		HW_Set_IF_Synthesizer(pObj, 0x002050);
		HW_Set_IF_Synthesizer(pObj, 0x1F8000);
		HW_Set_IF_Synthesizer(pObj, 0x1F8200);
		HW_Set_IF_Synthesizer(pObj, 0x1F8600);
		HW_Set_IF_Synthesizer(pObj, 0x1c0000);
		HW_Set_IF_Synthesizer(pObj, 0x10c458);

		HW_Set_IF_Synthesizer(pObj, 0x088e92);
		HW_Set_IF_Synthesizer(pObj, 0x187b82);
		HW_Set_IF_Synthesizer(pObj, 0x0401b4);
		HW_Set_IF_Synthesizer(pObj, 0x140816);
		HW_Set_IF_Synthesizer(pObj, 0x0c7000);
		HW_Set_IF_Synthesizer(pObj, 0x1c0000);
		HW_Set_IF_Synthesizer(pObj, 0x02ccae);
		HW_Set_IF_Synthesizer(pObj, 0x128023);
		HW_Set_IF_Synthesizer(pObj, 0x0a0000);
		HW_Set_IF_Synthesizer(pObj, GRF5101T[ChannelNo]);
		HW_Set_IF_Synthesizer(pObj, 0x06e380);
		HW_Set_IF_Synthesizer(pObj, 0x16cb94);
		HW_Set_IF_Synthesizer(pObj, 0x0e1740);
		HW_Set_IF_Synthesizer(pObj, 0x014980);
		HW_Set_IF_Synthesizer(pObj, 0x116240);
		HW_Set_IF_Synthesizer(pObj, 0x090000);
		HW_Set_IF_Synthesizer(pObj, 0x192304);
		HW_Set_IF_Synthesizer(pObj, 0x05112f);
		HW_Set_IF_Synthesizer(pObj, 0x0d54a8);
		HW_Set_IF_Synthesizer(pObj, 0x0f8000);
		HW_Set_IF_Synthesizer(pObj, 0x1c0008);
		HW_Set_IF_Synthesizer(pObj, 0x1c0000);

		HW_Set_IF_Synthesizer(pObj, GRF5101T[ChannelNo]);
		HW_Set_IF_Synthesizer(pObj, 0x1c0008);
		HW_Set_IF_Synthesizer(pObj, 0x150000);
		HW_Set_IF_Synthesizer(pObj, 0x0c7000);
		HW_Set_IF_Synthesizer(pObj, 0x150800);
		HW_Set_IF_Synthesizer(pObj, 0x150000);
	}	
	else{
		HW_Set_IF_Synthesizer(pObj, 0x1c0000);
		HW_Set_IF_Synthesizer(pObj, GRF5101T[ChannelNo]);

		HW_Set_IF_Synthesizer(pObj, 0x1c0008);
	}
}


void
HW_Set_AL2210MPVB_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
	void *reg = pObj->reg;
	U32	tmpvalue;

	pObj->SetReg(reg, ZD_PE1_PE2, 2);

	if (!InitChOnly){
		LockPhyReg(pObj);
		pObj->SetReg(reg, ZD_CR9, 0xe0);
		pObj->SetReg(reg, ZD_CR10, 0x91);
		pObj->SetReg(reg, ZD_CR12, 0x90);
		pObj->SetReg(reg, ZD_CR15, 0xd0);
		pObj->SetReg(reg, ZD_CR16, 0x40);
		pObj->SetReg(reg, ZD_CR17, 0x58);
		pObj->SetReg(reg, ZD_CR18, 0x04);
		pObj->SetReg(reg, ZD_CR23, 0x66);
		pObj->SetReg(reg, ZD_CR24, 0x14);
		pObj->SetReg(reg, ZD_CR26, 0x90);
		pObj->SetReg(reg, ZD_CR27, 0x30);
		pObj->SetReg(reg, ZD_CR31, 0x80);
		pObj->SetReg(reg, ZD_CR34, 0x06);
		pObj->SetReg(reg, ZD_CR35, 0x3e);
		pObj->SetReg(reg, ZD_CR38, 0x38);
		pObj->SetReg(reg, ZD_CR46, 0x90);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		pObj->SetReg(reg, ZD_CR64, 0x64);
		pObj->SetReg(reg, ZD_CR79, 0xb5);
		pObj->SetReg(reg, ZD_CR80, 0x38);
		pObj->SetReg(reg, ZD_CR81, 0x30);
		pObj->SetReg(reg, ZD_CR113, 0xc0);
		pObj->SetReg(reg, ZD_CR127, 0x03);
		UnLockPhyReg(pObj);
	
		HW_Set_IF_Synthesizer(pObj, AL2210TB[ChannelNo]);
		HW_Set_IF_Synthesizer(pObj, 0x00fcb1);
		HW_Set_IF_Synthesizer(pObj, 0x358132);
		HW_Set_IF_Synthesizer(pObj, 0x0108b3);
		HW_Set_IF_Synthesizer(pObj, 0xc77804);
		HW_Set_IF_Synthesizer(pObj, 0x456415);
		HW_Set_IF_Synthesizer(pObj, 0xff2226);
		HW_Set_IF_Synthesizer(pObj, 0x806667);
		HW_Set_IF_Synthesizer(pObj, 0x7860f8);
		HW_Set_IF_Synthesizer(pObj, 0xbb01c9);
		HW_Set_IF_Synthesizer(pObj, 0x00000A);
		HW_Set_IF_Synthesizer(pObj, 0x00000B);

		LockPhyReg(pObj);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		tmpvalue = pObj->GetReg(reg, ZD_RADIO_PD);

		tmpvalue &= ~BIT_0;
		pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
		tmpvalue |= BIT_0;
		pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
		pObj->SetReg(reg, ZD_RFCFG, 0x5);
		pObj->DelayUs(100);
		pObj->SetReg(reg, ZD_RFCFG, 0x0);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		UnLockPhyReg(pObj);
	}
	else {
		LockPhyReg(pObj);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		tmpvalue = pObj->GetReg(reg, ZD_RADIO_PD);
		tmpvalue &= ~BIT_0;

		pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
		tmpvalue |= BIT_0;



		pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
		pObj->SetReg(reg, ZD_RFCFG, 0x5);
		pObj->DelayUs(100);
		pObj->SetReg(reg, ZD_RFCFG, 0x0);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		UnLockPhyReg(pObj);
		HW_Set_IF_Synthesizer(pObj, AL2210TB[ChannelNo]);
	}		
	
	pObj->SetReg(reg, ZD_PE1_PE2, 3);
}


void
HW_Set_AL2210_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)

{
	void *reg = pObj->reg;
	U32	tmpvalue;

	pObj->SetReg(reg, ZD_PE1_PE2, 2);

	if (!InitChOnly){
		LockPhyReg(pObj);



		pObj->SetReg(reg, ZD_CR9, 0xe0);
		pObj->SetReg(reg, ZD_CR10, 0x91);
		pObj->SetReg(reg, ZD_CR12, 0x90);
		pObj->SetReg(reg, ZD_CR15, 0xd0);
		pObj->SetReg(reg, ZD_CR16, 0x40);
		pObj->SetReg(reg, ZD_CR17, 0x58);
		pObj->SetReg(reg, ZD_CR18, 0x04);
		pObj->SetReg(reg, ZD_CR23, 0x66);
		pObj->SetReg(reg, ZD_CR24, 0x14);

		pObj->SetReg(reg, ZD_CR26, 0x90);

		pObj->SetReg(reg, ZD_CR31, 0x80);
		pObj->SetReg(reg, ZD_CR34, 0x06);
		pObj->SetReg(reg, ZD_CR35, 0x3e);
		pObj->SetReg(reg, ZD_CR38, 0x38);
		pObj->SetReg(reg, ZD_CR46, 0x90);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		pObj->SetReg(reg, ZD_CR64, 0x64);
		pObj->SetReg(reg, ZD_CR79, 0xb5);
		pObj->SetReg(reg, ZD_CR80, 0x38);
		pObj->SetReg(reg, ZD_CR81, 0x30);
		pObj->SetReg(reg, ZD_CR113, 0xc0);
		pObj->SetReg(reg, ZD_CR127, 0x3);
		UnLockPhyReg(pObj);
	
		HW_Set_IF_Synthesizer(pObj, AL2210TB[ChannelNo]);

		HW_Set_IF_Synthesizer(pObj, 0x00fcb1);
		HW_Set_IF_Synthesizer(pObj, 0x358132);
		HW_Set_IF_Synthesizer(pObj, 0x0108b3);
		HW_Set_IF_Synthesizer(pObj, 0xc77804);
		HW_Set_IF_Synthesizer(pObj, 0x456415);
		HW_Set_IF_Synthesizer(pObj, 0xff2226);
		HW_Set_IF_Synthesizer(pObj, 0x806667);
		HW_Set_IF_Synthesizer(pObj, 0x7860f8);
		HW_Set_IF_Synthesizer(pObj, 0xbb01c9);
		HW_Set_IF_Synthesizer(pObj, 0x00000A);
		HW_Set_IF_Synthesizer(pObj, 0x00000B);

		LockPhyReg(pObj);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		tmpvalue = pObj->GetReg(reg, ZD_RADIO_PD);
		tmpvalue &= ~BIT_0;
		pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);

		tmpvalue |= BIT_0;
		pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
		pObj->SetReg(reg, ZD_RFCFG, 0x5);
		pObj->DelayUs(100);
		pObj->SetReg(reg, ZD_RFCFG, 0x0);
 		pObj->SetReg(reg, ZD_CR47, 0x1E);
		UnLockPhyReg(pObj);
	}
	else {
		LockPhyReg(pObj);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		tmpvalue = pObj->GetReg(reg, ZD_RADIO_PD);
		tmpvalue &= ~BIT_0;
		pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
		tmpvalue |= BIT_0;
		pObj->SetReg(reg, ZD_RADIO_PD, tmpvalue);
		pObj->SetReg(reg, ZD_RFCFG, 0x5);
		pObj->DelayUs(100);
		pObj->SetReg(reg, ZD_RFCFG, 0x0);
 		pObj->SetReg(reg, ZD_CR47, 0x1E);
		UnLockPhyReg(pObj);
		HW_Set_IF_Synthesizer(pObj, AL2210TB[ChannelNo]);
	}		

	pObj->SetReg(reg, ZD_PE1_PE2, 3);
}
*/
#if ZDCONF_RF_UW2453_SUPPORT == 1
//------------------------------------------------------------------------------
// Procedure:	 HW_Set_UW2453_RF_Chips
//
// Description:  
//
// Arguments:
//		Adapter - ptr to Adapter object instance
//		ChannelNo
//		Initial Channel only
//
// Returns:		(none)
//
// Note:
//-------------------------------------------------------------------------------
void
HW_Set_UW2453_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
    U32       tmpvalue;
    U32       ChannelNo_temp;
    int         i;
    BOOLEAN     bLocked;
    void *reg = pObj->reg;

#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
    pObj->SetReg(reg, PE1_PE2, 2);
#else
    //LockPhyReg(pObj);
    //pObj->GetReg(reg, ZD_CR203, &tmpvalue);
    //tmpvalue &= ~BIT_4;
    //pObj->SetReg(reg, ZD_CR203, tmpvalue);
    //UnLockPhyReg(pObj);
#endif
/*
    if(pObj->UW2453MiniCard)
    {
        if(pObj->UW2453NoTXfollowRX)
        {
            LockPhyReg(pObj);
            if(pObj->CardSetting.BSSType != PSEUDO_IBSS)
            {
                if(!pObj->UWDeafaltAntennt)
                {
                    if(!(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1]))
                    {
                        ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe0);
                    }
                    if(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1])
                    {
                        ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe4);
                    }
                }
                else
                {
                    if(!(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1]))
                    {
                        ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe4);  
                    }
                    if(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1])
                    {
                        ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe0);
                    }
                }
                pObj->UW2453SWDeafaultAntenna = TRUE;
                    
            }
            UnLockPhyReg(pObj);
        }
    }
*/
    if (!InitChOnly){
        LockPhyReg(pObj);
        pObj->SetReg(reg, ZD_CR10, 0x89);      
        pObj->SetReg(reg, ZD_CR15, 0x20);
        pObj->SetReg(reg, ZD_CR17, 0x28);  //6112  no change
        pObj->SetReg(reg, ZD_CR23, 0x38);
        pObj->SetReg(reg, ZD_CR24, 0x20);
        pObj->SetReg(reg, ZD_CR26, 0x93);
        pObj->SetReg(reg, ZD_CR27, 0x15);
        pObj->SetReg(reg, ZD_CR28, 0x3e);
        pObj->SetReg(reg, ZD_CR29, 0x00);
        pObj->SetReg(reg, ZD_CR33, 0x28);
        pObj->SetReg(reg, ZD_CR34, 0x30);
        pObj->SetReg(reg, ZD_CR35, 0x43);  //6112 3E->43
        pObj->SetReg(reg, ZD_CR41, 0x24);
        pObj->SetReg(reg, ZD_CR44, 0x32);
        pObj->SetReg(reg, ZD_CR46, 0x92);  //6112 96->92
        //pObj->SetReg(reg, ZD_CR47, 0x1E);
        pObj->SetReg(reg, ZD_CR48, 0x04);  //5602 Roger
        pObj->SetReg(reg, ZD_CR49, 0xfa);
        pObj->SetReg(reg, ZD_CR79, 0x58);
        pObj->SetReg(reg, ZD_CR80, 0x30);
        pObj->SetReg(reg, ZD_CR81, 0x30);
        pObj->SetReg(reg, ZD_CR87, 0x0A);
        pObj->SetReg(reg, ZD_CR89, 0x04);
        pObj->SetReg(reg, ZD_CR91, 0x00);
        pObj->SetReg(reg, ZD_CR92, 0x0a);
        pObj->SetReg(reg, ZD_CR98, 0x8d);
        pObj->SetReg(reg, ZD_CR99, 0x28);
        pObj->SetReg(reg, ZD_CR100, 0x02);
        pObj->SetReg(reg, ZD_CR101, 0x09);  //6112 13->1f //6220 1f->13 //6407 13->9
        pObj->SetReg(reg, ZD_CR102, 0x27);
        pObj->SetReg(reg, ZD_CR106, 0x1c);  //5d07 //6112 1f->1c //6220 1c->1f //6221 1f->1c
        pObj->SetReg(reg, ZD_CR107, 0x1c);  //6220 1c->1a //6221 1a->1c
        pObj->SetReg(reg, ZD_CR109, 0x13);
        pObj->SetReg(reg, ZD_CR110, 0x1f);  //6112 13->1f //6221 1f->13 //6407 13->0x09
        pObj->SetReg(reg, ZD_CR111, 0x13);
        pObj->SetReg(reg, ZD_CR112, 0x1f);
        pObj->SetReg(reg, ZD_CR113, 0x27);
        pObj->SetReg(reg, ZD_CR114, 0x23); //6221 27->23
        pObj->SetReg(reg, ZD_CR115, 0x24); //6112 24->1c //6220 1c->24
        pObj->SetReg(reg, ZD_CR116, 0x24); //6220 1c->24
        pObj->SetReg(reg, ZD_CR117, 0xfa);   //6112 fa->f8 //6220 f8->f4 //6220 f4->fa
        pObj->SetReg(reg, ZD_CR118, 0xf0);   //5d07  //6112 f0->f2 //6220 f2->f0
        pObj->SetReg(reg, ZD_CR119, 0x1a);  //6112 1a->10 //6220 10->14 //6220 14->1a
        pObj->SetReg(reg, ZD_CR120, 0x4f);
        pObj->SetReg(reg, ZD_CR121, 0x1f); //6220 4f->1f
        pObj->SetReg(reg, ZD_CR122, 0xf0);
        pObj->SetReg(reg, ZD_CR123, 0x57);
        pObj->SetReg(reg, ZD_CR125, 0xad);
        pObj->SetReg(reg, ZD_CR126, 0x6c);
        pObj->SetReg(reg, ZD_CR127, 0x03);
        pObj->SetReg(reg, ZD_CR128, 0x14); //6302 12->11
        pObj->SetReg(reg, ZD_CR129, 0x12); //6301 10->0F
        pObj->SetReg(reg, ZD_CR130, 0x10); 
        pObj->SetReg(reg, ZD_CR137, 0x50);
        pObj->SetReg(reg, ZD_CR138, 0xa8);
        pObj->SetReg(reg, ZD_CR144, 0xac);
        pObj->SetReg(reg, ZD_CR146, 0x20);

        pObj->SetReg(reg, ZD_CR252, 0xff);
        pObj->SetReg(reg, ZD_CR253, 0xff);
                
        UnLockPhyReg(pObj);
                                    
        HW_Set_IF_Synthesizer(pObj, 0x40002b); 
        HW_Set_IF_Synthesizer(pObj, 0x519e4f);
        //Set_IF_Synthesizer(Adapter, 0x509e4f);     //5d02                            
        HW_Set_IF_Synthesizer(pObj, 0x6f81AD);      //6221    6f81ac-> 6f81ff   //6418       6f81ff ->   6f81ac         
        HW_Set_IF_Synthesizer(pObj, 0x73fffe);                                 
        //Set_IF_Synthesizer(Adapter, 0x025fcc);   // 5d01    cal_fil 
        HW_Set_IF_Synthesizer(pObj, 0x025f9c);     // 5d01    cal_fil 
                            
        HW_Set_IF_Synthesizer(pObj, 0x100047);                                 
        HW_Set_IF_Synthesizer(pObj, 0x200999); 
        HW_Set_IF_Synthesizer(pObj, 0x307602);    //5d01  
                                        
        HW_Set_IF_Synthesizer(pObj, 0x346063);
        HW_Set_IF_Synthesizer(pObj, 0x025f98);    //idle                             
        HW_Set_IF_Synthesizer(pObj, 0x025f9a);    //cal_vco    
        HW_Set_IF_Synthesizer(pObj, 0x025f94);    //rxtx_en (4)
        HW_Set_IF_Synthesizer(pObj, 0x027FD4);
        //Set_IF_Synthesizer(Adapter, 0x307602);    //5d01  //6109

        //Auto Lock RF Procedure
        pObj->UW2453RFTableIndex=0;
        bLocked=FALSE;
        for (i=0;i<10;i++) {
            //always try channel 1
/*
            if(pObj->UW2453MiniCard)
            {
                Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3]); 
                Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3+1]);   
                Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3+2]);   
            }
            else
*/
            {
                HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3]);   
                HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3+1]); 
                HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3+2]); 
            }
            //ack interrupt event
            pObj->SetReg(reg, 0x85C1, 0x0F);
            //ZD1211_WRITE_REGISTER(Adapter, 0x85C1, 0x0F, FALSE);
            tmpvalue = pObj->GetReg(reg, 0x85C1);
            //ZD1211_READ_REGISTER(Adapter, 0x85C1, &tmpvalue, FALSE);
            if ((tmpvalue & 0xf) == 0x0 ) {
                bLocked=TRUE;
                pObj->UW2453RFTableIndex = i+1;
                break;
            }
        }
        if(!bLocked)
        {
            pObj->UW2453RFTableIndex = i+1;
        }


        //if (bLocked) {    
/*
        if(pObj->UW2453MiniCard)
        {
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3]);   
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3+1]); 
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3+2]); 
        }
        else
*/
        {
            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3]); 
            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3+1]);   
            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3+2]);   
        }
        //} else {  //turn off RF when we can't lock
        //  Set_IF_Synthesizer(Adapter, 0x025f90);  
        //  LockPhyReg(pObj);
        //  ZD1205_WRITE_REGISTER(Adapter, CR11, 0x04);
        //  ZD1205_WRITE_REGISTER(Adapter, CR251, 0x2f); 
        //  UnLockPhyReg(pObj);            
        //}

    }
    else{   
          //Set_IF_Synthesizer(Adapter, 0x40002b);//6109
          //Set_IF_Synthesizer(Adapter, 0x519e4f);//6109
          //Set_IF_Synthesizer(Adapter, 0x6f81ac);//6109
          //Set_IF_Synthesizer(Adapter, 0x73fffe);//6109
          //Set_IF_Synthesizer(Adapter, 0x025f9c);//6109
          //Set_IF_Synthesizer(Adapter, 0x025fcc);     // 5d01 //6109
/*
          if(pObj->UW2453MiniCard)
          {
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3]);
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3+1]);
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3+2]);
          }
          else
*/
          {
            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3]);
            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3+1]);
            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3+2]);
          }
          //Set_IF_Synthesizer(Adapter, 0x340060);
          HW_Set_IF_Synthesizer(pObj, 0x025f98);   //5d02
          HW_Set_IF_Synthesizer(pObj, 0x025f9a);  
          HW_Set_IF_Synthesizer(pObj, 0x025f94);
          HW_Set_IF_Synthesizer(pObj, 0x027FD4);
          //Set_IF_Synthesizer(Adapter, UW2453RF[ChannelNo*3+2]);  //5d02//6109
          
        
    }
    LockPhyReg(pObj);
    //Band Edge issue
    if(PURE_A_MODE != mMacMode)
    {
        if(pObj->HWFeature & BIT_21)
        {
            if(ChannelNo == 1 || ChannelNo == 11)
            {
                if(pObj->PHY_Decrease_CR128_state)
                {
                    pObj->SetReg(reg, ZD_CR128, 0x12);
                    pObj->SetReg(reg, ZD_CR129, 0x12);
                    pObj->SetReg(reg, ZD_CR130, 0x10);
                }
                else
                {
                    pObj->SetReg(reg, ZD_CR128, 0x10);
                    pObj->SetReg(reg, ZD_CR129, 0x10);
                    pObj->SetReg(reg, ZD_CR130, 0x10);
                }
            }
            else
            {
                pObj->SetReg(reg, ZD_CR128, 0x14);
                pObj->SetReg(reg, ZD_CR129, 0x12);
                pObj->SetReg(reg, ZD_CR130, 0x10);
            }
        }
        else
        {
            pObj->SetReg(reg, ZD_CR128, 0x14);
            pObj->SetReg(reg, ZD_CR129, 0x12);
            pObj->SetReg(reg, ZD_CR130, 0x10);
        }
    }
    pObj->SetReg(reg, ZD_CR80, 0x30);
    pObj->SetReg(reg, ZD_CR81, 0x30);
    pObj->SetReg(reg, ZD_CR79, 0x58);
    pObj->SetReg(reg, ZD_CR12, 0xF0);
    pObj->SetReg(reg, ZD_CR77, 0x1B);
    pObj->SetReg(reg, ZD_CR78, 0x58);

    UnLockPhyReg(pObj);
    //UW Tx Power
    for(i=0;i<19;i++)
    {
    if(pObj->IntValue[ChannelNo - 1] == ZD_UW2453TxGain[i].UWTxGainLevel)
        break;
    }
    if(i<19)
    {
        pObj->UWCurrentTxLevel = ZD_UW2453TxGain[i].UWTxGainLevel;
        pObj->UWDefaulTxLevel  = ZD_UW2453TxGain[i].UWTxGainLevel;
        PHY_UWTxPower(pObj, pObj->UWDefaulTxLevel);
    }
    LockPhyReg(pObj);
    //ZD1205_WRITE_REGISTER(Adapter, CR203, 0x06);
    pObj->SetReg(reg, ZD_CR203, 0x06);
    UnLockPhyReg(pObj);
    pObj->CR203Flag = 2;
    pObj->CR31Flag = 2;
    //pObj->PHY_G_BandEdge_Flag = 0;
    //pObj->UWStrongSingalFlag = 2;
    pObj->UW2453CCKSetFlag = 0;
    //pObj->UW24532MIssue  = 0;
}
#endif

#if ZDCONF_RF_AR2124_SUPPORT == 1
void
HW_Set_AR2124_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
    U32         tmpValue;
    U32         ChannelNo_temp;
    int         i;
    BOOLEAN     bLocked;
    void *reg = pObj->reg;	
	U16         WriteAddr[256];          
    U16         WriteData[256];  
	U16         WriteIndex = 0;

    //LockPhyReg(pObj);
    //pObj->GetReg(reg, ZD_CR203, &tmpvalue);
    //tmpValue &= ~BIT_4;
    //pObj->SetReg(reg, ZD_CR203, tmpvalue);
    //UnLockPhyReg(pObj);
/*
    if(pObj->UW2453MiniCard)
    {
        if(pObj->UW2453NoTXfollowRX)
        {
            LockPhyReg(pObj);
            if(pObj->CardSetting.BSSType != PSEUDO_IBSS)
            {
                if(!pObj->UWDeafaltAntennt)
                {
                    if(!(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1]))
                    {
                        ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe0);
                    }
                    if(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1])
                    {
                        ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe4);
                    }
                }
                else
                {
                    if(!(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1]))
                    {
                        ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe4);  
                    }
                    if(pObj->UW2453ChannelSelectAntennaAUX[ChannelNo-1])
                    {
                        ZD1205_WRITE_REGISTER(Adapter, CR9, 0xe0);
                    }
                }
                pObj->UW2453SWDeafaultAntenna = TRUE;
                    
            }
            UnLockPhyReg(pObj);
        }
    }
*/

	LockPhyReg(pObj);
	pObj->SetReg(reg, ZD_CR240, 0x57); // Turn on HW synthesiz control.
	UnLockPhyReg(pObj);

    // LockPhy	
	//tmpValue = pObj->GetReg(reg, CtlReg1);
	//tmpValue &= ~0x80;
	//pObj->SetReg(reg, CtlReg1, tmpValue);


	LockPhyReg(pObj);
    if (!InitChOnly){
        
        
        mFILL_WRITE_REGISTER( ZD_CR15, 0x20);
        mFILL_WRITE_REGISTER( ZD_CR10, 0x89);      
        mFILL_WRITE_REGISTER( ZD_CR15, 0x20);
        mFILL_WRITE_REGISTER( ZD_CR17, 0x28);  //6112  no change
        mFILL_WRITE_REGISTER( ZD_CR23, 0x38);
        mFILL_WRITE_REGISTER( ZD_CR24, 0x20);
        mFILL_WRITE_REGISTER( ZD_CR26, 0x93);
        mFILL_WRITE_REGISTER( ZD_CR27, 0x15);
        mFILL_WRITE_REGISTER( ZD_CR28, 0x3e);
        mFILL_WRITE_REGISTER( ZD_CR29, 0x00);
        mFILL_WRITE_REGISTER( ZD_CR33, 0x28);
        mFILL_WRITE_REGISTER( ZD_CR34, 0x30);
        mFILL_WRITE_REGISTER( ZD_CR35, 0x43);  //6112 3E->43
        mFILL_WRITE_REGISTER( ZD_CR41, 0x24);
        mFILL_WRITE_REGISTER( ZD_CR44, 0x32);
        mFILL_WRITE_REGISTER( ZD_CR46, 0x92);  //6112 96->92
        //mFILL_WRITE_REGISTER( ZD_CR47, 0x1E);
        mFILL_WRITE_REGISTER( ZD_CR48, 0x04);  //5602 Roger
        mFILL_WRITE_REGISTER( ZD_CR49, 0xfa);
        mFILL_WRITE_REGISTER( ZD_CR79, 0x58);
        mFILL_WRITE_REGISTER( ZD_CR80, 0x30);
        mFILL_WRITE_REGISTER( ZD_CR81, 0x30);
        mFILL_WRITE_REGISTER( ZD_CR87, 0x0A);
        mFILL_WRITE_REGISTER( ZD_CR89, 0x04);
        mFILL_WRITE_REGISTER( ZD_CR91, 0x00);
        mFILL_WRITE_REGISTER( ZD_CR92, 0x0a);
        mFILL_WRITE_REGISTER( ZD_CR98, 0x8d);
        mFILL_WRITE_REGISTER( ZD_CR99, 0x28);
        mFILL_WRITE_REGISTER( ZD_CR100, 0x02);
        mFILL_WRITE_REGISTER( ZD_CR101, 0x09);  //6112 13->1f //6220 1f->13 //6407 13->9
        mFILL_WRITE_REGISTER( ZD_CR102, 0x27);
        mFILL_WRITE_REGISTER( ZD_CR106, 0x1c);  //5d07 //6112 1f->1c //6220 1c->1f //6221 1f->1c
        mFILL_WRITE_REGISTER( ZD_CR107, 0x1c);  //6220 1c->1a //6221 1a->1c
        mFILL_WRITE_REGISTER( ZD_CR109, 0x13);
        mFILL_WRITE_REGISTER( ZD_CR110, 0x1f);  //6112 13->1f //6221 1f->13 //6407 13->0x09
        mFILL_WRITE_REGISTER( ZD_CR111, 0x13);
        mFILL_WRITE_REGISTER( ZD_CR112, 0x1f);
        mFILL_WRITE_REGISTER( ZD_CR113, 0x27);
        mFILL_WRITE_REGISTER( ZD_CR114, 0x23); //6221 27->23
        mFILL_WRITE_REGISTER( ZD_CR115, 0x24); //6112 24->1c //6220 1c->24
        mFILL_WRITE_REGISTER( ZD_CR116, 0x24); //6220 1c->24
        mFILL_WRITE_REGISTER( ZD_CR117, 0xfa);   //6112 fa->f8 //6220 f8->f4 //6220 f4->fa
        mFILL_WRITE_REGISTER( ZD_CR118, 0xf0);   //5d07  //6112 f0->f2 //6220 f2->f0
        mFILL_WRITE_REGISTER( ZD_CR119, 0x1a);  //6112 1a->10 //6220 10->14 //6220 14->1a
        mFILL_WRITE_REGISTER( ZD_CR120, 0x4f);
        mFILL_WRITE_REGISTER( ZD_CR121, 0x1f); //6220 4f->1f
        mFILL_WRITE_REGISTER( ZD_CR122, 0xf0);
        mFILL_WRITE_REGISTER( ZD_CR123, 0x57);
        mFILL_WRITE_REGISTER( ZD_CR125, 0xad);
        mFILL_WRITE_REGISTER( ZD_CR126, 0x6c);
        mFILL_WRITE_REGISTER( ZD_CR127, 0x03);
        mFILL_WRITE_REGISTER( ZD_CR128, 0x14); //6302 12->11
        mFILL_WRITE_REGISTER( ZD_CR129, 0x12); //6301 10->0F
        mFILL_WRITE_REGISTER( ZD_CR130, 0x10); 
        mFILL_WRITE_REGISTER( ZD_CR137, 0x50);
        mFILL_WRITE_REGISTER( ZD_CR138, 0xa8);
        mFILL_WRITE_REGISTER( ZD_CR144, 0xac);
        mFILL_WRITE_REGISTER( ZD_CR146, 0x20);
        
        mFILL_WRITE_REGISTER( ZD_CR252, 0xff);
        mFILL_WRITE_REGISTER( ZD_CR253, 0xff);
                
      
         
        
        SET_IF_SYNTHESIZER(macp, 0xd40002);  
		    SET_IF_SYNTHESIZER(macp, 0xf2798a);  
		    
		    SET_IF_SYNTHESIZER(macp, 0xb581f6);  
		    SET_IF_SYNTHESIZER(macp, 0x7fffce);
 		    
 		    SET_IF_SYNTHESIZER(macp, 0x39fa40);  
		    SET_IF_SYNTHESIZER(macp, 0xe20008);  
		    SET_IF_SYNTHESIZER(macp, 0x999004);  
		    SET_IF_SYNTHESIZER(macp, 0x406e0c);  
		    	                                      
		    SET_IF_SYNTHESIZER(macp, 0xc6062c);  
		    SET_IF_SYNTHESIZER(macp, 0x19fa40);  
		    SET_IF_SYNTHESIZER(macp, 0x59fa40);  
		    SET_IF_SYNTHESIZER(macp, 0x29fa40);  
		    SET_IF_SYNTHESIZER(macp, 0x2bfe40);  
            // Fix at 12th table
            pObj->UW2453RFTableIndex = 11;
        //HW_Set_IF_Synthesizer(pObj, 0x40002b); 
        //HW_Set_IF_Synthesizer(pObj, 0x519e4f);
        ////Set_IF_Synthesizer(Adapter, 0x509e4f);     //5d02                            
        //HW_Set_IF_Synthesizer(pObj, 0x6f81AD);      //6221    6f81ac-> 6f81ff   //6418       6f81ff ->   6f81ac         
        //HW_Set_IF_Synthesizer(pObj, 0x73fffe);                                 
        ////Set_IF_Synthesizer(Adapter, 0x025fcc);   // 5d01    cal_fil 
        //HW_Set_IF_Synthesizer(pObj, 0x025f9c);     // 5d01    cal_fil 
        //                    
        //HW_Set_IF_Synthesizer(pObj, 0x100047);                                 
        //HW_Set_IF_Synthesizer(pObj, 0x200999); 
        //HW_Set_IF_Synthesizer(pObj, 0x307602);    //5d01  
        //                                
        //HW_Set_IF_Synthesizer(pObj, 0x346063);
        //HW_Set_IF_Synthesizer(pObj, 0x025f98);    //idle                             
        //HW_Set_IF_Synthesizer(pObj, 0x025f9a);    //cal_vco    
        //HW_Set_IF_Synthesizer(pObj, 0x025f94);    //rxtx_en (4)
        //HW_Set_IF_Synthesizer(pObj, 0x027FD4);
        //Set_IF_Synthesizer(Adapter, 0x307602);    //5d01  //6109

//        //Auto Lock RF Procedure
//        pObj->UW2453RFTableIndex=0;
//        bLocked=FALSE;
//        for (i=0;i<10;i++) {
//            //always try channel 1
///*
//            if(pObj->UW2453MiniCard)
//            {
//                Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3]); 
//                Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3+1]);   
//                Set_IF_Synthesizer(Adapter, UW2453RF_minicard[i][1*3+2]);   
//            }
//            else
//*/
//            {
//                HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3]);   
//                HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3+1]); 
//                HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[i][1*3+2]); 
//            }
//            //ack interrupt event
//            pObj->SetReg(reg, 0x85C1, 0x0F);
//            //ZD1211_WRITE_REGISTER(Adapter, 0x85C1, 0x0F, FALSE);
//            tmpvalue = pObj->GetReg(reg, 0x85C1);
//            //ZD1211_READ_REGISTER(Adapter, 0x85C1, &tmpvalue, FALSE);
//            if ((tmpvalue & 0xf) == 0x0 ) {
//                bLocked=TRUE;
//                pObj->UW2453RFTableIndex = i+1;
//                break;
//            }
//        }
//        if(!bLocked)
//        {
//            pObj->UW2453RFTableIndex = i+1;
//        }
//
//
//        //if (bLocked) {    
///*
//        if(pObj->UW2453MiniCard)
//        {
//            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3]);   
//            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3+1]); 
//            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][1*3+2]); 
//        }
//        else
//*/
//        {
//            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3]); 
//            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3+1]);   
//            HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][1*3+2]);   
//        }
//        //} else {  //turn off RF when we can't lock
//        //  Set_IF_Synthesizer(Adapter, 0x025f90);  
//        //  LockPhyReg(pObj);
//        //  ZD1205_WRITE_REGISTER(Adapter, CR11, 0x04);
//        //  ZD1205_WRITE_REGISTER(Adapter, CR251, 0x2f); 
//        //  UnLockPhyReg(pObj);            
//        //}

    }
    else{   
          //Set_IF_Synthesizer(Adapter, 0x40002b);//6109
          //Set_IF_Synthesizer(Adapter, 0x519e4f);//6109
          //Set_IF_Synthesizer(Adapter, 0x6f81ac);//6109
          //Set_IF_Synthesizer(Adapter, 0x73fffe);//6109
          //Set_IF_Synthesizer(Adapter, 0x025f9c);//6109
          //Set_IF_Synthesizer(Adapter, 0x025fcc);     // 5d01 //6109
/*
          if(pObj->UW2453MiniCard)
          {
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3]);
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3+1]);
            Set_IF_Synthesizer(Adapter, UW2453RF_minicard[pObj->UW2453RFTableIndex][ChannelNo*3+2]);
          }
          else
*/
       //software 3-wire
       //   {
       //     HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3]);
       //     HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3+1]);
       //     HW_Set_IF_Synthesizer(pObj, UW2453RF_dongle[pObj->UW2453RFTableIndex][ChannelNo*3+2]);
       //   }
       //   //Set_IF_Synthesizer(Adapter, 0x340060);
       //   HW_Set_IF_Synthesizer(pObj, 0x025f98);   //5d02
       //   HW_Set_IF_Synthesizer(pObj, 0x025f9a);  
       //   HW_Set_IF_Synthesizer(pObj, 0x025f94);
       //   HW_Set_IF_Synthesizer(pObj, 0x027FD4);
       //   //Set_IF_Synthesizer(Adapter, UW2453RF[ChannelNo*3+2]);  //5d02//6109
                                                                                                  
        SET_IF_SYNTHESIZER(macp, UW2453RF_HW[11][ChannelNo*3]);
		SET_IF_SYNTHESIZER(macp, UW2453RF_HW[11][ChannelNo*3+1]);
		SET_IF_SYNTHESIZER(macp, UW2453RF_HW[11][ChannelNo*3+2]);
        //printk(KERN_DEBUG "SetCH %d %x %x %x\n", ChannelNo, UW2453RF_HW[11][ChannelNo*3], 
         //           UW2453RF_HW[11][ChannelNo*3+1],
           //         UW2453RF_HW[11][ChannelNo*3+2]
                    //);
		                                                     
        SET_IF_SYNTHESIZER(macp, 0x19fa40);
        SET_IF_SYNTHESIZER(macp, 0x59fa40); 
        ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);
#if 0
        UnLockPhyReg(pObj); //xxx123
	LockPhyReg(pObj);
	pObj->SetReg(reg, ZD_CR240, 0x80); // Turn off HW synthesize control.
    UnLockPhyReg(pObj); 
	LockPhyReg(pObj);
	pObj->SetReg(reg, ZD_CR240, 0x57); // Turn off HW synthesize control.
    UnLockPhyReg(pObj); 
	LockPhyReg(pObj);
#endif
        // Require a delay between two settings. 
        SET_IF_SYNTHESIZER(macp, 0x29fa40);  
		SET_IF_SYNTHESIZER(macp, 0x2bfe40); 
    }
    
    
    //mFILL_WRITE_REGISTER( ZD_CR203, 0x06);
    ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);
    UnLockPhyReg(pObj); 

	
    // UnlockPhy
	//tmpValue = pObj->GetReg(reg, CtlReg1);
	//tmpValue |= ~0x80;
	//pObj->SetReg(reg, CtlReg1, tmpValue);

	LockPhyReg(pObj);
	pObj->SetReg(reg, ZD_CR240, 0x80); // Turn off HW synthesize control.
    UnLockPhyReg(pObj); 
    
    LockPhyReg(pObj);
    //Band Edge issue
    if(PURE_A_MODE != mMacMode)
    {
        if(pObj->HWFeature & BIT_21)
        {
            if(ChannelNo == 1 || ChannelNo == 11)
            {
                if(pObj->PHY_Decrease_CR128_state)
                {
                    pObj->SetReg(reg, ZD_CR128, 0x12);
                    pObj->SetReg(reg, ZD_CR129, 0x12);
                    pObj->SetReg(reg, ZD_CR130, 0x10);
                }
                else
                {
                    pObj->SetReg(reg, ZD_CR128, 0x10);
                    pObj->SetReg(reg, ZD_CR129, 0x10);
                    pObj->SetReg(reg, ZD_CR130, 0x10);
                }
            }
            else
            {
                pObj->SetReg(reg, ZD_CR128, 0x14);
                pObj->SetReg(reg, ZD_CR129, 0x12);
                pObj->SetReg(reg, ZD_CR130, 0x10);
            }
        }
        else
        {
            pObj->SetReg(reg, ZD_CR128, 0x14);
            pObj->SetReg(reg, ZD_CR129, 0x12);
            pObj->SetReg(reg, ZD_CR130, 0x10);
        }
    }
    pObj->SetReg(reg, ZD_CR80, 0x30);
    pObj->SetReg(reg, ZD_CR81, 0x30);
    pObj->SetReg(reg, ZD_CR79, 0x58);
    pObj->SetReg(reg, ZD_CR12, 0xF0);
    pObj->SetReg(reg, ZD_CR77, 0x1B);
    pObj->SetReg(reg, ZD_CR78, 0x58);

    UnLockPhyReg(pObj);
    //UW Tx Power
    for(i=0;i<19;i++)
    {
        if(pObj->IntValue[ChannelNo - 1] == ZD_AR2124TxGain[i].UWTxGainLevel)
            break;
    }
    //printk(" IntValue: %d\n", pObj->IntValue[ChannelNo - 1]);
    
    if(i<19)
    {
        pObj->UWCurrentTxLevel = ZD_AR2124TxGain[i].UWTxGainLevel;
        pObj->UWDefaulTxLevel  = ZD_AR2124TxGain[i].UWTxGainLevel;
                
        PHY_UWTxPower(pObj, pObj->UWDefaulTxLevel);
    }

    LockPhyReg(pObj);
    pObj->SetReg(reg, ZD_CR203, 0x06);
    UnLockPhyReg(pObj);

    pObj->CR203Flag = 2;
    pObj->CR31Flag = 2;
    //pObj->PHY_G_BandEdge_Flag = 0;
    //pObj->UWStrongSingalFlag = 2;
    pObj->UW2453CCKSetFlag = 0;
    //pObj->UW24532MIssue  = 0;
}
#endif
#if ZDCONF_RF_UW2453_SUPPORT ==  1 || ZDCONF_RF_AR2124_SUPPORT == 1
void UW2453_AR2124_StrongSigCounterMeasureOnOff(zd_80211Obj_t *pObj, int onOff)
{
    if(onOff == 1)
    {
        LockPhyReg(pObj);
        pObj->SetReg(pObj->reg, ZD_CR17, 0x69);
        pObj->SetReg(pObj->reg, ZD_CR27, 0x1f);
        pObj->SetReg(pObj->reg, ZD_CR35, 0x6b);
        pObj->SetReg(pObj->reg, ZD_CR46, 0x12);
        pObj->SetReg(pObj->reg, ZD_CR113, 0x23);
        pObj->SetReg(pObj->reg, ZD_CR127, 0x1);
        UnLockPhyReg(pObj);
    }
    else
    {
        LockPhyReg(pObj);
        pObj->SetReg(pObj->reg, ZD_CR17, 0x28);
        pObj->SetReg(pObj->reg, ZD_CR27, 0x15);
        pObj->SetReg(pObj->reg, ZD_CR35, 0x43);
        pObj->SetReg(pObj->reg, ZD_CR46, 0x92);
        pObj->SetReg(pObj->reg, ZD_CR113, 0x27);
        pObj->SetReg(pObj->reg, ZD_CR127, 0x3);
        UnLockPhyReg(pObj);
    }
}
#endif

#if ZDCONF_RF_AL7230B_SUPPORT == 1
//------------------------------------------------------------------------------
// Procedure:	 HW_Set_AL7230B_Chips
//
// Description:  
//
// Arguments:
//		Adapter - ptr to Adapter object instance
//		ChannelNo
//		Initial Channel only
//
// Returns:		(none)
//
// Note:
//-------------------------------------------------------------------------------
#ifndef ZD1211B
// 1211
void HW_Set_AL7230B_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly, U8 MAC_Mode)
{
	void	*reg = pObj->reg;
	U32		tmpValue;
	U32		ChannelNo_temp;
	//int     i;
	static u8 mOldMacMode = MIXED_MODE;
	U16     WriteAddr[256];          
    U16     WriteData[256];  
	U16     WriteIndex = 0;
	
	LockPhyReg(pObj);
	pObj->SetReg(reg, ZD_CR240, 0x57);
	UnLockPhyReg(pObj);
	
	tmpValue = pObj->GetReg(reg, CtlReg1);
	tmpValue &= ~0x80;
	pObj->SetReg(reg, CtlReg1, tmpValue);

	if (!InitChOnly){
		mFILL_WRITE_REGISTER( ZD_CR15, 0x20);
		mFILL_WRITE_REGISTER( ZD_CR23, 0x40);
		mFILL_WRITE_REGISTER( ZD_CR24, 0x20);
		mFILL_WRITE_REGISTER( ZD_CR26, 0x11);
		mFILL_WRITE_REGISTER( ZD_CR28, 0x3e);
		mFILL_WRITE_REGISTER( ZD_CR29, 0x00);
		mFILL_WRITE_REGISTER( ZD_CR44, 0x33);
		mFILL_WRITE_REGISTER( ZD_CR106, 0x22);  //from 0x2a to 0x22 for AL7230B
		mFILL_WRITE_REGISTER( ZD_CR107, 0x1a);
		mFILL_WRITE_REGISTER( ZD_CR109, 0x9);
		mFILL_WRITE_REGISTER( ZD_CR110, 0x27);
		mFILL_WRITE_REGISTER( ZD_CR111, 0x2b);  
		mFILL_WRITE_REGISTER( ZD_CR112, 0x2b);
		mFILL_WRITE_REGISTER( ZD_CR119, 0xa);
		mFILL_WRITE_REGISTER( ZD_CR122, 0xfc); //from /e0 to fc for AL7230B
		mFILL_WRITE_REGISTER( ZD_CR10, 0x89);		
		mFILL_WRITE_REGISTER( ZD_CR17, 0x28);  
		mFILL_WRITE_REGISTER( ZD_CR26, 0x93);
		mFILL_WRITE_REGISTER( ZD_CR34, 0x30);
		mFILL_WRITE_REGISTER( ZD_CR35, 0x3E);  
		mFILL_WRITE_REGISTER( ZD_CR41, 0x24);
		mFILL_WRITE_REGISTER( ZD_CR44, 0x32);
		mFILL_WRITE_REGISTER( ZD_CR46, 0x96);  
		mFILL_WRITE_REGISTER( ZD_CR47, 0x1e);
		mFILL_WRITE_REGISTER( ZD_CR79, 0x58);
		mFILL_WRITE_REGISTER( ZD_CR80, 0x30);
		mFILL_WRITE_REGISTER( ZD_CR81, 0x30);
		mFILL_WRITE_REGISTER( ZD_CR87, 0x0A);
		mFILL_WRITE_REGISTER( ZD_CR89, 0x04);
		mFILL_WRITE_REGISTER( ZD_CR92, 0x0a);
		mFILL_WRITE_REGISTER( ZD_CR99, 0x28);
		mFILL_WRITE_REGISTER( ZD_CR100, 0x02);
		mFILL_WRITE_REGISTER( ZD_CR101, 0x13);
		mFILL_WRITE_REGISTER( ZD_CR102, 0x27);
		mFILL_WRITE_REGISTER( ZD_CR106, 0x22); //from 0x20 to 0x22 for AL7230B
		mFILL_WRITE_REGISTER( ZD_CR107, 0x3f);
		mFILL_WRITE_REGISTER( ZD_CR109, 0x09);
		mFILL_WRITE_REGISTER( ZD_CR110, 0x1f);  
		mFILL_WRITE_REGISTER( ZD_CR111, 0x1f);
		mFILL_WRITE_REGISTER( ZD_CR112, 0x1f);
		mFILL_WRITE_REGISTER( ZD_CR113, 0x27);
		mFILL_WRITE_REGISTER( ZD_CR114, 0x27);
		mFILL_WRITE_REGISTER( ZD_CR115, 0x24);  
		mFILL_WRITE_REGISTER( ZD_CR116, 0x3f);
		mFILL_WRITE_REGISTER( ZD_CR117, 0xfa);
		mFILL_WRITE_REGISTER( ZD_CR118, 0xfc);
		mFILL_WRITE_REGISTER( ZD_CR119, 0x10);
		mFILL_WRITE_REGISTER( ZD_CR120, 0x4f);
		mFILL_WRITE_REGISTER( ZD_CR121, 0x77);
		mFILL_WRITE_REGISTER( ZD_CR137, 0x88);
		mFILL_WRITE_REGISTER( ZD_CR138, 0xa8);
		mFILL_WRITE_REGISTER( ZD_CR252, 0x34);
		mFILL_WRITE_REGISTER( ZD_CR253, 0x34);
       // mFILL_WRITE_REGISTER( ZD_CR240, 0x57);

		if( MAC_Mode != PURE_A_MODE )
		{
			mFILL_WRITE_REGISTER( ZD_CR251, 0x2f);  //PLL_OFF
			SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2]);
			SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2+1]);
			//SET_IF_SYNTHESIZER(macp, 0x8cccd0);
			SET_IF_SYNTHESIZER(macp, 0x4ff821);
			SET_IF_SYNTHESIZER(macp, 0xc5fbfc);
			SET_IF_SYNTHESIZER(macp, 0x21ebfe);  
			SET_IF_SYNTHESIZER(macp, 0xafd401);  //freq shift 0xaad401
			SET_IF_SYNTHESIZER(macp, 0x6cf56a);  
			SET_IF_SYNTHESIZER(macp, 0xe04073); 
			SET_IF_SYNTHESIZER(macp, 0x193d76);
			SET_IF_SYNTHESIZER(macp, 0x9dd844);  
			SET_IF_SYNTHESIZER(macp, 0x500007);  
			SET_IF_SYNTHESIZER(macp, 0xd8c010);  
			SET_IF_SYNTHESIZER(macp, 0x3c9000);  
			//Adapter->AL7230CCKSetFlag=0;	
			SET_IF_SYNTHESIZER(macp, 0xbfffff); 
			SET_IF_SYNTHESIZER(macp, 0x700000); 
			SET_IF_SYNTHESIZER(macp, 0xf15d58);
			//AcquireCtrOfPhyReg(Adapter);
			//ZD1205_WRITE_REGISTER(Adapter, CR251, 0x2f);  //PLL_OFF
			mFILL_WRITE_REGISTER( ZD_CR251, 0x3f);  //PLL_ON
			mFILL_WRITE_REGISTER( ZD_CR128, 0x14);
			mFILL_WRITE_REGISTER( ZD_CR129, 0x12);
			mFILL_WRITE_REGISTER( ZD_CR130, 0x10);
			mFILL_WRITE_REGISTER( ZD_CR38, 0x38);
			mFILL_WRITE_REGISTER( ZD_CR136, 0xdf);
			///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
			///NdisStallExecution(1000);
			SET_IF_SYNTHESIZER(macp, 0xf15d59);
			///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
			///NdisStallExecution(10000);
			SET_IF_SYNTHESIZER(macp, 0xf15d5c);
			///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
			///NdisStallExecution(10000);
			SET_IF_SYNTHESIZER(macp, 0xf15d58);
		}
		else
		{
			mFILL_WRITE_REGISTER( ZD_CR251, 0x2f); // shdnb(PLL_ON)=0		
			if((34 <= ChannelNo) && (ChannelNo <= 48)){
				ChannelNo_temp=(ChannelNo/2)-13;		
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
			}
			else{
				ChannelNo_temp=(ChannelNo/4)-1;
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
			}
			SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
			SET_IF_SYNTHESIZER(macp, 0x47f8a2);
			SET_IF_SYNTHESIZER(macp, 0xc5fbfa);
			//SET_IF_SYNTHESIZER(macp, 0x21ebf6);  
			SET_IF_SYNTHESIZER(macp, 0xaafca1);  
			SET_IF_SYNTHESIZER(macp, 0x6cf56a);  
			SET_IF_SYNTHESIZER(macp, 0xe04073); 
			SET_IF_SYNTHESIZER(macp, 0x193d76);
			SET_IF_SYNTHESIZER(macp, 0x9dd844);  
			SET_IF_SYNTHESIZER(macp, 0x500607);  
			SET_IF_SYNTHESIZER(macp, 0xd8c010);
			if((48 < ChannelNo) && (ChannelNo < 184)){												
				SET_IF_SYNTHESIZER(macp, 0x3c2800); 
			}
			else{
				SET_IF_SYNTHESIZER(macp, 0x3e2800); 
			}
			SET_IF_SYNTHESIZER(macp, 0xbfffff); 
			SET_IF_SYNTHESIZER(macp, 0x700000); 
			SET_IF_SYNTHESIZER(macp, 0xf35d48);
			//AcquireCtrOfPhyReg(Adapter);
			//ZD1205_WRITE_REGISTER(Adapter, CR251, 0x2f); // shdnb(PLL_ON)=0
			mFILL_WRITE_REGISTER( ZD_CR251, 0x3f); // shdnb(PLL_ON)=1  
			mFILL_WRITE_REGISTER( ZD_CR128, 0x12);
			mFILL_WRITE_REGISTER( ZD_CR129, 0x10);
			mFILL_WRITE_REGISTER( ZD_CR130, 0x10);
			mFILL_WRITE_REGISTER( ZD_CR38, 0x7f);
			mFILL_WRITE_REGISTER( ZD_CR136, 0x5f);
            ///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
			///NdisStallExecution(1000);
			SET_IF_SYNTHESIZER(macp, 0xf15d59);
			///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
			///NdisStallExecution(10000);
			SET_IF_SYNTHESIZER(macp, 0xf15d5c);
			///ZD1211_WRITE_MULTI_REG(Adapter, WriteAddr, WriteData, &WriteIndex);
			///NdisStallExecution(10000);
			SET_IF_SYNTHESIZER(macp, 0xf35d48);
		}

	}
	else{
		if( MAC_Mode != PURE_A_MODE )
		{
			mFILL_WRITE_REGISTER( ZD_CR251, 0x2f);  //PLL_OFF
			//SET_IF_SYNTHESIZER(macp, 0x0b3331);
			if ( 1 || mOldMacMode != MAC_Mode )
			{
				SET_IF_SYNTHESIZER(macp, 0x4ff821);
				SET_IF_SYNTHESIZER(macp, 0xc5fbfc);
				SET_IF_SYNTHESIZER(macp, 0x21ebfe);  
				SET_IF_SYNTHESIZER(macp, 0xafd401);  //fix freq shift, 0xaad401
				SET_IF_SYNTHESIZER(macp, 0x6cf56a);  
				SET_IF_SYNTHESIZER(macp, 0xe04073); 
				SET_IF_SYNTHESIZER(macp, 0x193d76);
				SET_IF_SYNTHESIZER(macp, 0x9dd844);  
				SET_IF_SYNTHESIZER(macp, 0x500007);  
				SET_IF_SYNTHESIZER(macp, 0xd8c010);  
				SET_IF_SYNTHESIZER(macp, 0x3c9000);  
				SET_IF_SYNTHESIZER(macp, 0xf15d58);

				mFILL_WRITE_REGISTER( ZD_CR128, 0x14);
				mFILL_WRITE_REGISTER( ZD_CR129, 0x12);
				mFILL_WRITE_REGISTER( ZD_CR130, 0x10);
				mFILL_WRITE_REGISTER( ZD_CR38, 0x38);
				mFILL_WRITE_REGISTER( ZD_CR136, 0xdf);
				mOldMacMode = MAC_Mode;
			}
			//Adapter->AL7230CCKSetFlag=0;	
			SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2]);
			SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2+1]);
			SET_IF_SYNTHESIZER(macp, 0x3c9000);
			mFILL_WRITE_REGISTER( ZD_CR251, 0x3f);  //PLL_ON
		}
		else
		{ 
			mFILL_WRITE_REGISTER( ZD_CR251, 0x2f); // shdnb(PLL_ON)=0

			if ( 1 || mOldMacMode != MAC_Mode )
			{
				SET_IF_SYNTHESIZER(macp, 0x47f8a2);
				SET_IF_SYNTHESIZER(macp, 0xc5fbfa);
				SET_IF_SYNTHESIZER(macp, 0xaafca1);  
				SET_IF_SYNTHESIZER(macp, 0x6cf56a);  
				SET_IF_SYNTHESIZER(macp, 0xe04073); 
				SET_IF_SYNTHESIZER(macp, 0x193d76);
				SET_IF_SYNTHESIZER(macp, 0x9dd844);  
				SET_IF_SYNTHESIZER(macp, 0x500607);  
				SET_IF_SYNTHESIZER(macp, 0xd8c010);		
				SET_IF_SYNTHESIZER(macp, 0xf35d48);
				mFILL_WRITE_REGISTER( ZD_CR128, 0x12);
				mFILL_WRITE_REGISTER( ZD_CR129, 0x10);
				mFILL_WRITE_REGISTER( ZD_CR130, 0x10);
				mFILL_WRITE_REGISTER( ZD_CR38, 0x7f);
				mFILL_WRITE_REGISTER( ZD_CR136, 0x5f);
				mOldMacMode = MAC_Mode;
			}

			if((48 < ChannelNo) && (ChannelNo < 184))
			{
				SET_IF_SYNTHESIZER(macp, 0x3c2800); 
			}
			else
			{
				SET_IF_SYNTHESIZER(macp, 0x3e2800); 
			}

			if((34 <= ChannelNo) && (ChannelNo <= 48))
			{
				ChannelNo_temp=(ChannelNo/2)-13;		
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
			}
			else
			{
				ChannelNo_temp=(ChannelNo/4)-1;
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
				SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
			}

			mFILL_WRITE_REGISTER( ZD_CR251, 0x3f);  //PLL_ON			
		}

	}

	mFILL_WRITE_REGISTER( ZD_CR203, 0x06);
    ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);

	

	tmpValue = pObj->GetReg(reg, CtlReg1);
	tmpValue |= ~0x80;
	pObj->SetReg(reg, CtlReg1, tmpValue);

	LockPhyReg(pObj);
	pObj->SetReg(reg, ZD_CR240, 0x80);
	
	pObj->CR203Flag = 2;
    if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
    {
        tmpValue = pObj->GetReg(reg, E2P_PHY_REG);
        pObj->SetReg(reg, ZD_CR47, (tmpValue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
    }
    if (pObj->HWFeature & BIT_21)  //6321 for FCC regulation, enabled per HWFeature 6M band edge bit (for AL2230, AL2230S)
    {
        if (ChannelNo == 1 || ChannelNo == 11)  //MARK_003, band edge, these may depend on PCB layout
        {
            pObj->SetReg(reg, ZD_CR128, 0x12);
            pObj->SetReg(reg, ZD_CR129, 0x12);
            pObj->SetReg(reg, ZD_CR130, 0x10);
            pObj->SetReg(reg, ZD_CR47, 0x1E);
        }
        else //(ChannelNo 2 ~ 10, 12 ~ 14)
        {
            pObj->SetReg(reg, ZD_CR128, 0x14);
            pObj->SetReg(reg, ZD_CR129, 0x12);
            pObj->SetReg(reg, ZD_CR130, 0x10);
            pObj->SetReg(reg, ZD_CR47, 0x1E);
        }
    }

    UnLockPhyReg(pObj);

//	pObj->CR31Flag = 2;
 //   macp->PHY_G_6M_BandEdge_Flag = 0;
//	if(macp->PHY_36M_Setpoint_Flag != 0)
//	{
//		for(i=0;i<16;i++)
//			macp->a_Calibration_Data[2][i] = macp->PHY_36M_A_Calibration_Setpoint[i];
//		for(i=0;i<32;i++)
//			macp->a_Interpolation_Data[2][i] = macp->PHY_36M_A_Interpolation_Setpoint[i];
//		macp->PHY_36M_Setpoint_Flag = 0;
//	}
		
}
#else
// 1211B
void HW_Set_AL7230B_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly, U8 MAC_Mode)
{

    void *reg = pObj->reg;
    U32       tmpvalue;
    U32       ChannelNo_temp;
    int         i;
    U16      WriteAddr[256];          
    U16      WriteData[256];  
    U16      WriteIndex = 0;
    LockPhyReg(pObj);
    pObj->SetReg(reg, ZD_CR240, 0x57);
    if (1) //(!pObj->CurrentAntenna) // 0-->Main
        pObj->SetReg(reg, ZD_CR9, 0xe4);
    else
        pObj->SetReg(reg, ZD_CR9, 0xe0);
    UnLockPhyReg(pObj);
    tmpvalue = pObj->GetReg(pObj,CtlReg1);
    tmpvalue &= ~0x80;
    pObj->SetReg(reg, CtlReg1, tmpvalue);


    if (!InitChOnly){
        //mFILL_WRITE_REGISTER(ZD_CR9, 0xe0);//5119
        mFILL_WRITE_REGISTER(ZD_CR10, 0x8B);
        mFILL_WRITE_REGISTER(ZD_CR15, 0x20);
        mFILL_WRITE_REGISTER(ZD_CR17, 0x2B);//for newest(3rd cut)AL2230
        mFILL_WRITE_REGISTER(ZD_CR20, 0x10);//4N25->Stone Request
        mFILL_WRITE_REGISTER(ZD_CR23, 0x40);
        mFILL_WRITE_REGISTER(ZD_CR24, 0x20);
        mFILL_WRITE_REGISTER(ZD_CR26, 0x93);
        mFILL_WRITE_REGISTER(ZD_CR28, 0x3e);
        mFILL_WRITE_REGISTER(ZD_CR29, 0x00);
        mFILL_WRITE_REGISTER(ZD_CR33, 0x28);   //5613
        mFILL_WRITE_REGISTER(ZD_CR34, 0x30);
        mFILL_WRITE_REGISTER(ZD_CR35, 0x3e);  //for newest(3rd cut) AL2230
        mFILL_WRITE_REGISTER(ZD_CR41, 0x24);
        mFILL_WRITE_REGISTER(ZD_CR44, 0x32);
        mFILL_WRITE_REGISTER(ZD_CR46, 0x99);  //for newest(3rd cut) AL2230  
        mFILL_WRITE_REGISTER(ZD_CR47, 0x1e);
        mFILL_WRITE_REGISTER(ZD_CR48, 0x00);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR49, 0x00);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR51, 0x01);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR52, 0x80);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR53, 0x7e);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR65, 0x00);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR66, 0x00);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR67, 0x00);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR68, 0x00);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR69, 0x28);   //ZD1215 5610
        mFILL_WRITE_REGISTER(ZD_CR79, 0x58);
        mFILL_WRITE_REGISTER(ZD_CR80, 0x30);
        mFILL_WRITE_REGISTER(ZD_CR81, 0x30);
        mFILL_WRITE_REGISTER(ZD_CR87, 0x0A);
        mFILL_WRITE_REGISTER(ZD_CR89, 0x04);
        mFILL_WRITE_REGISTER(ZD_CR90, 0x58);  //5112
        mFILL_WRITE_REGISTER(ZD_CR91, 0x00);  //5613
        mFILL_WRITE_REGISTER(ZD_CR92, 0x0a);
        mFILL_WRITE_REGISTER(ZD_CR98, 0x8d);  //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR99, 0x00);
        mFILL_WRITE_REGISTER(ZD_CR100, 0x02);
        mFILL_WRITE_REGISTER(ZD_CR101, 0x13);
        mFILL_WRITE_REGISTER(ZD_CR102, 0x27);
        mFILL_WRITE_REGISTER(ZD_CR106, 0x20);  // change to 0x24 for AL7230B
        mFILL_WRITE_REGISTER(ZD_CR109, 0x13);  //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR112, 0x1f);
        if(pObj->PHYNEWLayout)
        {
            mFILL_WRITE_REGISTER(ZD_CR107, 0x28);
            mFILL_WRITE_REGISTER(ZD_CR110, 0x1f);  //5127, 0x13->0x1f
            mFILL_WRITE_REGISTER(ZD_CR111, 0x1f);  //0x13 to 0x1f for AL7230B
            mFILL_WRITE_REGISTER(ZD_CR116, 0x2a);
            mFILL_WRITE_REGISTER(ZD_CR118, 0xfa); 
            mFILL_WRITE_REGISTER(ZD_CR119, 0x12);
            mFILL_WRITE_REGISTER(ZD_CR121, 0x6c);  //5613
        }
        else
        {
            mFILL_WRITE_REGISTER(ZD_CR107, 0x24);
            mFILL_WRITE_REGISTER(ZD_CR110, 0x13);  //5127, 0x13->0x1f
            mFILL_WRITE_REGISTER(ZD_CR111, 0x13);  //0x13 to 0x1f for AL7230B
            mFILL_WRITE_REGISTER(ZD_CR116, 0x24);
            mFILL_WRITE_REGISTER(ZD_CR118, 0xfc); 
            mFILL_WRITE_REGISTER(ZD_CR119, 0x11);
            mFILL_WRITE_REGISTER(ZD_CR121, 0x6a);  //5613
        }
        mFILL_WRITE_REGISTER(ZD_CR113, 0x27);
        mFILL_WRITE_REGISTER(ZD_CR114, 0x27);  
        mFILL_WRITE_REGISTER(ZD_CR115, 0x24);
        mFILL_WRITE_REGISTER(ZD_CR117, 0xfa);
        mFILL_WRITE_REGISTER(ZD_CR120, 0x4f);
        mFILL_WRITE_REGISTER(ZD_CR122, 0xfc);  // E0->FCh at 4901
        mFILL_WRITE_REGISTER(ZD_CR123, 0x57);  //5613
        mFILL_WRITE_REGISTER(ZD_CR125, 0xad);  //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR126, 0x6c);  //5613
        mFILL_WRITE_REGISTER(ZD_CR127, 0x03);  //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
        mFILL_WRITE_REGISTER(ZD_CR131, 0x00);   //5112
        mFILL_WRITE_REGISTER(ZD_CR137, 0x50);   //5613
        mFILL_WRITE_REGISTER(ZD_CR138, 0xa8);  //5112
        mFILL_WRITE_REGISTER(ZD_CR144, 0xac);  //5613
        mFILL_WRITE_REGISTER(ZD_CR148, 0x40);   //5112
        mFILL_WRITE_REGISTER(ZD_CR149, 0x40);  //4O07, 50->40
        mFILL_WRITE_REGISTER(ZD_CR150, 0x1a);  //5112, 0C->1A
        

        mFILL_WRITE_REGISTER(ZD_CR252, 0x34);
        mFILL_WRITE_REGISTER(ZD_CR253, 0x34);
        //mFILL_WRITE_REGISTER(ZD_CR240, 0x57);
        if( mMacMode != PURE_A_MODE)
        {
            mFILL_WRITE_REGISTER(ZD_CR251, 0x2f);  //PLL_OFF
            SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2]);
            SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2+1]);
            //SET_IF_SYNTHESIZER(macp, 0x8cccd0);
            SET_IF_SYNTHESIZER(macp, 0x4ff821);
            SET_IF_SYNTHESIZER(macp, 0xc5fbfc);
            SET_IF_SYNTHESIZER(macp, 0x21ebfe);  
            SET_IF_SYNTHESIZER(macp, 0xafd401);  
            SET_IF_SYNTHESIZER(macp, 0x6cf56a);  
            SET_IF_SYNTHESIZER(macp, 0xe04073); 
            SET_IF_SYNTHESIZER(macp, 0x190d76);
            SET_IF_SYNTHESIZER(macp, 0x9dd844);  
            SET_IF_SYNTHESIZER(macp, 0x500007);  
            SET_IF_SYNTHESIZER(macp, 0xd8c010);  
            SET_IF_SYNTHESIZER(macp, 0x3c9000);  
            //pObj->AL7230CCKSetFlag=0;    
            SET_IF_SYNTHESIZER(macp, 0xbfffff); 
            SET_IF_SYNTHESIZER(macp, 0x700000); 
            SET_IF_SYNTHESIZER(macp, 0xf15d58);
            //LockPhyReg(pObj);
            //mFILL_WRITE_REGISTER(ZD_CR251, 0x2f);  //PLL_OFF
            mFILL_WRITE_REGISTER(ZD_CR251, 0x7f);  //PLL_ON
            mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
            mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
            mFILL_WRITE_REGISTER(ZD_CR38, 0x38);
            mFILL_WRITE_REGISTER(ZD_CR136, 0xdf);
            //NdisStallExecution(1000);
            SET_IF_SYNTHESIZER(macp, 0xf15d59);
            //NdisStallExecution(10000);
            SET_IF_SYNTHESIZER(macp, 0xf15d5c);
            //NdisStallExecution(10000);
            SET_IF_SYNTHESIZER(macp, 0xf15d58);
        }
        else
        {
            mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); // shdnb(PLL_ON)=0       
            if((34 <= ChannelNo) && (ChannelNo <= 48)){
                ChannelNo_temp=(ChannelNo/2)-13;        
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
            }
            else{
                ChannelNo_temp=(ChannelNo/4)-1;
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
            }
            SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
            SET_IF_SYNTHESIZER(macp, 0x47f8a2);
            SET_IF_SYNTHESIZER(macp, 0xc5fbfa);
            //SET_IF_SYNTHESIZER(macp, 0x21ebf6);  
            SET_IF_SYNTHESIZER(macp, 0xaffca1);  
            SET_IF_SYNTHESIZER(macp, 0x6cf56a);  
            SET_IF_SYNTHESIZER(macp, 0xe04073); 
            SET_IF_SYNTHESIZER(macp, 0x190d36);
            SET_IF_SYNTHESIZER(macp, 0x9dd844);  
            SET_IF_SYNTHESIZER(macp, 0x500607);  
            SET_IF_SYNTHESIZER(macp, 0xd8c010);
            if((48 < ChannelNo) && (ChannelNo < 184)){                                              
                SET_IF_SYNTHESIZER(macp, 0x3c2800); 
            }
            else{
                SET_IF_SYNTHESIZER(macp, 0x3e2800); 
            }
            SET_IF_SYNTHESIZER(macp, 0xbfffff); 
            SET_IF_SYNTHESIZER(macp, 0x700000); 
            SET_IF_SYNTHESIZER(macp, 0xf35d48);
            //LockPhyReg(pObj);
            //mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
            mFILL_WRITE_REGISTER(ZD_CR251, 0x7f); // shdnb(PLL_ON)=1  
            mFILL_WRITE_REGISTER(ZD_CR128, 0x12);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
            mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
            mFILL_WRITE_REGISTER(ZD_CR38, 0x7f);
            mFILL_WRITE_REGISTER(ZD_CR136, 0x5f);
            //mFILL_WRITE_REGISTER(ZD_CR31, 0x58);
            
            //NdisStallExecution(1000);
            SET_IF_SYNTHESIZER(macp, 0xf15d59);
            //NdisStallExecution(10000);
            SET_IF_SYNTHESIZER(macp, 0xf15d5c);
            //NdisStallExecution(10000);
            SET_IF_SYNTHESIZER(macp, 0xf35d48);
        }

    }
    else{
        if( mMacMode != PURE_A_MODE)
        {
            mFILL_WRITE_REGISTER(ZD_CR251, 0x2f);  //PLL_OFF
            //Set_IF_Synthesizer(Adapter, 0x8cccd0);
            if (1)//pObj->OldNetworkType != pObj->CardSetting.NetworkTypeInUse )
            {
            SET_IF_SYNTHESIZER(macp, 0x4ff821);
            SET_IF_SYNTHESIZER(macp, 0xc5fbfc);
            SET_IF_SYNTHESIZER(macp, 0x21ebfe);  
            SET_IF_SYNTHESIZER(macp, 0xafd401);  
            SET_IF_SYNTHESIZER(macp, 0x6cf56a);  
            SET_IF_SYNTHESIZER(macp, 0xe04073); 
            SET_IF_SYNTHESIZER(macp, 0x190d76);
            SET_IF_SYNTHESIZER(macp, 0x9dd844);  
            SET_IF_SYNTHESIZER(macp, 0x500007);  
            SET_IF_SYNTHESIZER(macp, 0xd8c010);  
            SET_IF_SYNTHESIZER(macp, 0x3c9000);  
            SET_IF_SYNTHESIZER(macp, 0xf15d58);
            //LockPhyReg(pObj);
            //mFILL_WRITE_REGISTER(ZD_CR251, 0x2f);  //PLL_OFF
            //mFILL_WRITE_REGISTER(ZD_CR251, 0x3f);  //PLL_ON
            mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
            mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
            mFILL_WRITE_REGISTER(ZD_CR38, 0x38);
            mFILL_WRITE_REGISTER(ZD_CR136, 0xdf);
            //pObj->OldNetworkType = pObj->CardSetting.NetworkTypeInUse;
            }
            //pObj->AL7230CCKSetFlag=0;    
            SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2]);
            SET_IF_SYNTHESIZER(macp, AL7230BTB[ChannelNo*2+1]);
            SET_IF_SYNTHESIZER(macp, 0x3c9000);
            mFILL_WRITE_REGISTER(ZD_CR251, 0x7f);  //PLL_ON
            
            //NdisStallExecution(10);
            //SET_IF_SYNTHESIZER(macp, 0xf15d59);
            //NdisStallExecution(100);
            //SET_IF_SYNTHESIZER(macp, 0xf15d5c);
            //NdisStallExecution(100);
            //SET_IF_SYNTHESIZER(macp, 0xf15d58);
        }
        else
        {           
            mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
            SET_IF_SYNTHESIZER(macp, 0x190d36);

            if (1)//pObj->OldNetworkType != pObj->CardSetting.NetworkTypeInUse )
            {
            SET_IF_SYNTHESIZER(macp, 0x47f8a2);
            SET_IF_SYNTHESIZER(macp, 0xc5fbfa);
            //SET_IF_SYNTHESIZER(macp, 0x21ebf6);  
            SET_IF_SYNTHESIZER(macp, 0xaffca1);  
            SET_IF_SYNTHESIZER(macp, 0x6cf56a);  
            SET_IF_SYNTHESIZER(macp, 0xe04073); 
            //SET_IF_SYNTHESIZER(macp, 0x190d36);
            SET_IF_SYNTHESIZER(macp, 0x9dd844);  
            SET_IF_SYNTHESIZER(macp, 0x500607);  
            SET_IF_SYNTHESIZER(macp, 0xd8c010);      
            SET_IF_SYNTHESIZER(macp, 0xf35d48);
            //LockPhyReg(pObj);
            //mFILL_WRITE_REGISTER(ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
            //mFILL_WRITE_REGISTER(ZD_CR251, 0x3f); // shdnb(PLL_ON)=1  
            mFILL_WRITE_REGISTER(ZD_CR128, 0x12);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
            mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
            mFILL_WRITE_REGISTER(ZD_CR38, 0x7f);
            mFILL_WRITE_REGISTER(ZD_CR136, 0x5f);
            //pObj->OldNetworkType = pObj->CardSetting.NetworkTypeInUse;
            }
            if((48 < ChannelNo) && (ChannelNo < 184)){                                              
                SET_IF_SYNTHESIZER(macp, 0x3c2800); 
            }
            else{
                SET_IF_SYNTHESIZER(macp, 0x3e2800); 
            }   
            if((34 <= ChannelNo) && (ChannelNo <= 48)){
                ChannelNo_temp=(ChannelNo/2)-13;        
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
                //SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+2]);
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
                   // SET_IF_SYNTHESIZER(macp, 0x3c2800);
            }
            else{
                ChannelNo_temp=(ChannelNo/4)-1;
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4]);
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+1]);
                //SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+2]);
                SET_IF_SYNTHESIZER(macp, AL7230BTB_a[ChannelNo_temp*4+3]);
                //SET_IF_SYNTHESIZER(macp, 0x3c2800);
            }
            mFILL_WRITE_REGISTER(ZD_CR251, 0x7f);  //PLL_ON
            //ZD1205_WRITE_REGISTER(Adapter, CR31, 0x58);
            
            //NdisStallExecution(10);
            //SET_IF_SYNTHESIZER(macp, 0xf15d59);
            //NdisStallExecution(100);
            //SET_IF_SYNTHESIZER(macp, 0xf15d5c);
            //NdisStallExecution(100);
            //SET_IF_SYNTHESIZER(macp, 0xf35d58);
        }

    }
#if ZDCONF_ADHOC_SUPPORT == 1
    if(mBssType == INDEPENDENT_BSS)
    {
        mFILL_WRITE_REGISTER(ZD_CR80, 0x0C);
        mFILL_WRITE_REGISTER(ZD_CR81, 0x0C);
        mFILL_WRITE_REGISTER(ZD_CR79, 0x16);
        mFILL_WRITE_REGISTER(ZD_CR12, 0x54);
        mFILL_WRITE_REGISTER(ZD_CR77, 0x1B);
        mFILL_WRITE_REGISTER(ZD_CR78, 0x58);
    }
    else
#endif
    {
        mFILL_WRITE_REGISTER(ZD_CR80, 0x30);
        mFILL_WRITE_REGISTER(ZD_CR81, 0x30);
        mFILL_WRITE_REGISTER(ZD_CR79, 0x58);
        mFILL_WRITE_REGISTER(ZD_CR12, 0xF0);
        mFILL_WRITE_REGISTER(ZD_CR77, 0x1B);
        mFILL_WRITE_REGISTER(ZD_CR78, 0x58);
    }

    if(pObj->HWFeature & BIT_21)
    {
        if(ChannelNo == 1)
        {
            mFILL_WRITE_REGISTER(ZD_CR128, 0x0e);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
        }
        else if(ChannelNo == 11)
        {
            mFILL_WRITE_REGISTER(ZD_CR128, 0x10);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
        }
        else if(ChannelNo != 1 && ChannelNo != 11)
        {
            mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
        }
    }
    //pObj->SetReg(reg, ZD_CR138, 0x28);
    mFILL_WRITE_REGISTER(ZD_CR203, 0x04);
    ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);

    tmpvalue = pObj->GetReg(reg ,CtlReg1);
    tmpvalue |= 0x80;
    pObj->SetReg(reg, CtlReg1, tmpvalue);

    LockPhyReg(pObj);

    pObj->SetReg(reg, ZD_CR240, 0x80);
    if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
    {
        tmpvalue = pObj->GetReg(reg, E2P_PHY_REG);
        pObj->SetReg(reg, ZD_CR47, (tmpvalue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
    }
    if(pObj->PHYNEWLayout)
    {
        if (1)//!pObj->CurrentAntenna) // CurrentAntenna = 0 ->Main
            pObj->SetReg(reg, ZD_CR9, 0xe5);
        else
            pObj->SetReg(reg, ZD_CR9, 0xe1);
    }
    pObj->SetReg(reg, ZD_CR203, 0x04);
    UnLockPhyReg(pObj);
    pObj->CR203Flag = 2;
    pObj->CR31Flag = 2;
    //pObj->Change_SetPoint = 2;
    //pObj->PHY_G_6M_BandEdge_Flag = 0;
/*
    if(pObj->PHY_36M_Setpoint_Flag != 0)
    {
        //for(i=0;i<14;i++)
        //  pObj->SetPointOFDM[0][i] = pObj->PHY_36M_G_Setpoint[i]; 
        for(i=0;i<16;i++)
            pObj->a_Calibration_Data[2][i] = pObj->PHY_36M_A_Calibration_Setpoint[i];
        for(i=0;i<32;i++)
            pObj->a_Interpolation_Data[2][i] = pObj->PHY_36M_A_Interpolation_Setpoint[i];
        pObj->PHY_36M_Setpoint_Flag = 0;
    }
*/

#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
    pObj->SetReg(reg, PE1_PE2, 3);
#endif



}

// end of AL7230B ZD1215
#endif
#endif //End ZDCONF_RF_AL7230B_SUPPORT
#if ZDCONF_RF_AL2232_SUPPORT == 1
//------------------------------------------------------------------------------
// Procedure:    HW_Set_AL2232_Chips
//
// Description:
//
// Arguments:
//      pObj - ptr to Adapter object instance
//      ChannelNo
//      Initial Channel only
//
// Returns:     (none)
//
// Note:
//-------------------------------------------------------------------------------
void
HW_Set_AL2232_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
    void *reg = pObj->reg;
    struct zd1205_private *macp = (struct zd1205_private *)netdev_priv(g_dev);
    U32 tmpValue;

    if (!InitChOnly)
    {
        LockPhyReg(pObj);
        pObj->SetReg(reg,ZD_CR9, 0xE0);           //5119
        pObj->SetReg(reg,ZD_CR15, 0x20);
        pObj->SetReg(reg,ZD_CR23, 0x40);
        pObj->SetReg(reg,ZD_CR24, 0x20);
        pObj->SetReg(reg,ZD_CR26, 0x11);
        pObj->SetReg(reg,ZD_CR28, 0x3e);
        pObj->SetReg(reg,ZD_CR29, 0x00);
        pObj->SetReg(reg,ZD_CR44, 0x33);
        pObj->SetReg(reg,ZD_CR106, 0x22);         // 2004/10/19  0x2a -> 0x22
        pObj->SetReg(reg,ZD_CR107, 0x1a);
        pObj->SetReg(reg,ZD_CR109, 0x9);
        pObj->SetReg(reg,ZD_CR110, 0x27);
        pObj->SetReg(reg,ZD_CR111, 0x2b);
        pObj->SetReg(reg,ZD_CR112, 0x2b);
        pObj->SetReg(reg,ZD_CR119, 0xa);

        pObj->SetReg(reg,ZD_CR10, 0x89);
        pObj->SetReg(reg,ZD_CR17, 0x2B);          //for newest(3rd cut) AL2230
        pObj->SetReg(reg,ZD_CR20, 0x12);          //4N25 -> Stone Request
        pObj->SetReg(reg,ZD_CR26, 0x93);
        pObj->SetReg(reg,ZD_CR34, 0x30);
        pObj->SetReg(reg,ZD_CR35, 0x3E);          //for newest(3rd cut) AL2230
        pObj->SetReg(reg,ZD_CR41, 0x24);
        pObj->SetReg(reg,ZD_CR44, 0x32);
        pObj->SetReg(reg,ZD_CR46, 0x99);          //for newest(3rd cut) AL2230
        pObj->SetReg(reg,ZD_CR47, 0x1e);
        pObj->SetReg(reg,ZD_CR79, 0x58);
        pObj->SetReg(reg,ZD_CR80, 0x30);
        pObj->SetReg(reg,ZD_CR81, 0x30);
        pObj->SetReg(reg,ZD_CR87, 0x0A);
        pObj->SetReg(reg,ZD_CR89, 0x04);
        pObj->SetReg(reg,ZD_CR90, 0x58);          //5113
        pObj->SetReg(reg,ZD_CR92, 0x0a);
        pObj->SetReg(reg,ZD_CR98, 0x8d);          //4804, for 1212 new algorithm
        pObj->SetReg(reg,ZD_CR99, 0x28);
        pObj->SetReg(reg,ZD_CR100, 0x00);
        pObj->SetReg(reg,ZD_CR101, 0x13);
        pObj->SetReg(reg,ZD_CR102, 0x27);
        pObj->SetReg(reg,ZD_CR106, 0x22);         //for newest(3rd cut) AL2230
                                                  // 2004/10/19  0x2a -> 0x22
        pObj->SetReg(reg,ZD_CR107, 0x2A);
        pObj->SetReg(reg,ZD_CR109, 0x13);         //4804, for 1212 new algorithm
        pObj->SetReg(reg,ZD_CR110, 0x1F);         //4804, for 1212 new algorithm
        pObj->SetReg(reg,ZD_CR111, 0x1F);         //4804, for 1212 new algorithm
        pObj->SetReg(reg,ZD_CR112, 0x1f);
        pObj->SetReg(reg,ZD_CR113, 0x27);
        pObj->SetReg(reg,ZD_CR114, 0x27);
        pObj->SetReg(reg,ZD_CR115, 0x26);         //24->26 at 4901
        pObj->SetReg(reg,ZD_CR116, 0x24);         // 26->24 at 4901
   //rk     pObj->SetReg(reg,ZD_CR117, 0xfa);
        pObj->SetReg(reg,ZD_CR118, 0xf8);         //4O07, fa->f8
        pObj->SetReg(reg,ZD_CR119, 0x10);
        pObj->SetReg(reg,ZD_CR120, 0x4f);
        pObj->SetReg(reg,ZD_CR121, 0x0a);         //4804, for 1212 new algorithm
        pObj->SetReg(reg,ZD_CR122, 0xFC);         // E0->FCh at 4901
        pObj->SetReg(reg,ZD_CR125, 0xaD);         //4804, for 1212 new algorithm
        pObj->SetReg(reg,ZD_CR127, 0x03);         //4804, for 1212 new algorithm
        pObj->SetReg(reg,ZD_CR137, 0x88);
        pObj->SetReg(reg,ZD_CR131, 0x00);         //5113
        pObj->SetReg(reg,ZD_CR148, 0x40);         //5113
        pObj->SetReg(reg,ZD_CR149, 0x40);         //4O07, 50->40
        pObj->SetReg(reg,ZD_CR150, 0x1A);         //5113, 0C->1A

        pObj->SetReg(reg,ZD_CR252, 0x34);
        pObj->SetReg(reg,ZD_CR253, 0x34);

        UnLockPhyReg(pObj);

        HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3]);
        HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3+1]);
        HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3+2]);
        HW_Set_IF_Synthesizer(pObj, 0x0b3331);
        HW_Set_IF_Synthesizer(pObj, 0x01b802);
        HW_Set_IF_Synthesizer(pObj, 0x00fff3);
        HW_Set_IF_Synthesizer(pObj, 0x0005a4);
        HW_Set_IF_Synthesizer(pObj, 0x044dc5);
        HW_Set_IF_Synthesizer(pObj, 0x0805b6);
        HW_Set_IF_Synthesizer(pObj, 0x0146C7);
        HW_Set_IF_Synthesizer(pObj, 0x000688);
        HW_Set_IF_Synthesizer(pObj, 0x0403b9);
        HW_Set_IF_Synthesizer(pObj, 0x00dbba);
        HW_Set_IF_Synthesizer(pObj, 0x00099b);
        HW_Set_IF_Synthesizer(pObj, 0x0bdffc);
        HW_Set_IF_Synthesizer(pObj, 0x00000d);
        HW_Set_IF_Synthesizer(pObj, 0x00580f);

        LockPhyReg(pObj);
        pObj->SetReg(reg, ZD_CR251, 0x2f);        // shdnb(PLL_ON)=0
        pObj->DelayUs(10);
        UnLockPhyReg(pObj);

//HW_Set_IF_Synthesizer(pObj, 0x000d00f);
        HW_Set_IF_Synthesizer(pObj, 0x000d80f);
        pObj->DelayUs(100);
        HW_Set_IF_Synthesizer(pObj, 0x00780f);
        pObj->DelayUs(100);
//HW_Set_IF_Synthesizer(pObj, 0x00500f);
        HW_Set_IF_Synthesizer(pObj, 0x00580f);
    }
    else
    {
        HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3]);
        HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3+1]);
        HW_Set_IF_Synthesizer(pObj, AL2232TB[ChannelNo*3+2]);
    }

    LockPhyReg(pObj);
    if (1 )//|| macp->bContinueTx == 0)           // Do not modify CR203 during CAL mode
    {
        pObj->SetReg(reg, ZD_CR203, 0x06);
    }
    
    if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
    {
        tmpValue = pObj->GetReg(reg, E2P_PHY_REG);
        pObj->SetReg(reg, ZD_CR47, (tmpValue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
    }
    
    #if 0 //6321 TO DO
    if (pObj->HWFeature & BIT_22)  //6321 High power band edge for FCC regulation, enabled per HWFeature
    {
        if (ChannelNo == 1 || ChannelNo == 11) //these may depend on PCB layout
        {
            pObj->SetReg(reg, ZD_CR128, );
            pObj->SetReg(reg, ZD_CR129, );
            pObj->SetReg(reg, ZD_CR130, );
            pObj->SetReg(reg, ZD_CR47, );
        }
        else //(ChannelNo 2 ~ 10, 12 ~ 14)
        {
            pObj->SetReg(reg, ZD_CR128, );
            pObj->SetReg(reg, ZD_CR129, );
            pObj->SetReg(reg, ZD_CR130, );
            pObj->SetReg(reg, ZD_CR47, );
        }
    }
    #endif
    
    UnLockPhyReg(pObj);

    pObj->CR203Flag = 2;
    pObj->CR31Flag = 2;                           //cCR31InitialState;

}
#endif // ZDCONF_RF_AL2232_SUPPORT
#if ZDCONF_RF_AL2230_SUPPORT == 1
#ifdef ZD1211 
void
HW_Set_AL2230_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{

	void *reg = pObj->reg;
	U32	tmpvalue;


	if (!InitChOnly){
		LockPhyReg(pObj);
#ifdef ZD1211B
		pObj->SetReg(reg, ZD_CR10, 0x89);
#endif
		pObj->SetReg(reg, ZD_CR15, 0x20);
#ifdef ZD1211B
        pObj->SetReg(reg, ZD_CR17, 0x2B);
#endif
		pObj->SetReg(reg, ZD_CR23, 0x40);
		pObj->SetReg(reg, ZD_CR24, 0x20);
#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR26, 0x11);
#elif defined(ZD1211B)
		pObj->SetReg(reg, ZD_CR26, 0x93);
#endif
		pObj->SetReg(reg, ZD_CR28, 0x3e);
		pObj->SetReg(reg, ZD_CR29, 0x00);
#ifdef ZD1211B
		pObj->SetReg(reg, ZD_CR33, 0x28);
#elif defined(ZD1211)
		pObj->SetReg(reg, ZD_CR44, 0x33);
		pObj->SetReg(reg, ZD_CR106, 0x2a);
		pObj->SetReg(reg, ZD_CR107, 0x1a);
		pObj->SetReg(reg, ZD_CR109, 0x9);
		pObj->SetReg(reg, ZD_CR110, 0x27);
		pObj->SetReg(reg, ZD_CR111, 0x2b);
		pObj->SetReg(reg, ZD_CR112, 0x2b);
		pObj->SetReg(reg, ZD_CR119, 0xa);
#endif

#if (defined(GCCK) && defined(OFDM))
		pObj->SetReg(reg, ZD_CR10, 0x89);
		pObj->SetReg(reg, ZD_CR17, 0x28); //for newest (3rd cut) AL2300
		pObj->SetReg(reg, ZD_CR26, 0x93);
		pObj->SetReg(reg, ZD_CR34, 0x30);
		pObj->SetReg(reg, ZD_CR35, 0x3E); //for newest (3rd cut) AL2300
		pObj->SetReg(reg, ZD_CR41, 0x24);

#ifdef HOST_IF_USB
		pObj->SetReg(reg, ZD_CR44, 0x32);
#else
		pObj->SetReg(reg, ZD_CR44, 0x32);
#endif
		pObj->SetReg(reg, ZD_CR46, 0x96); //for newest (3rd cut) AL2300
		pObj->SetReg(reg, ZD_CR47, 0x1e);
#ifdef ZD1211B
		pObj->SetReg(reg,ZD_CR48, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR49, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR51, 0x01);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR52, 0x80);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR53, 0x7e);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR65, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR66, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR67, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR68, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR69, 0x28);		//ZD1211B 05.06.10
#endif
		pObj->SetReg(reg, ZD_CR79, 0x58);
		pObj->SetReg(reg, ZD_CR80, 0x30);
		pObj->SetReg(reg, ZD_CR81, 0x30);
		pObj->SetReg(reg, ZD_CR87, 0x0A);
		pObj->SetReg(reg, ZD_CR89, 0x04);


		pObj->SetReg(reg, ZD_CR92, 0x0a);
		pObj->SetReg(reg, ZD_CR99, 0x28);
		pObj->SetReg(reg, ZD_CR100, 0x00);
		pObj->SetReg(reg, ZD_CR101, 0x13);
		pObj->SetReg(reg, ZD_CR102, 0x27);
		pObj->SetReg(reg, ZD_CR106, 0x24);
		pObj->SetReg(reg, ZD_CR107, 0x2A);
		pObj->SetReg(reg, ZD_CR109, 0x09);
		pObj->SetReg(reg, ZD_CR110, 0x13);
		pObj->SetReg(reg, ZD_CR111, 0x1f);
		pObj->SetReg(reg, ZD_CR112, 0x1f);
		pObj->SetReg(reg, ZD_CR113, 0x27);
		pObj->SetReg(reg, ZD_CR114, 0x27);
		pObj->SetReg(reg, ZD_CR115, 0x24); //for newest (3rd cut) AL2300
		pObj->SetReg(reg, ZD_CR116, 0x24);
#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR117, 0xf4);
		pObj->SetReg(reg, ZD_CR118, 0xfc);
#elif defined(ZD1211B)
        pObj->SetReg(reg, ZD_CR117, 0xfa);
        pObj->SetReg(reg, ZD_CR118, 0xfa);
#endif
		pObj->SetReg(reg, ZD_CR119, 0x10);
		pObj->SetReg(reg, ZD_CR120, 0x4f);
#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR121, 0x77);
		pObj->SetReg(reg, ZD_CR122, 0xe0);
#elif defined(ZD1211B)
        pObj->SetReg(reg, ZD_CR121, 0x6c);
        pObj->SetReg(reg, ZD_CR122, 0xfc);
#endif
		pObj->SetReg(reg, ZD_CR137, 0x88);
#ifndef HOST_IF_USB
		pObj->SetReg(reg, ZD_CR150, 0x0D);
#endif
#elif (defined(ECCK_60_5))
		pObj->SetReg(reg, ZD_CR47, 0x1E);
		pObj->SetReg(reg, ZD_CR106, 0x04);
		pObj->SetReg(reg, ZD_CR107, 0x00);
		pObj->SetReg(reg, ZD_CR14, 0x80);
		pObj->SetReg(reg, ZD_CR10, 0x89);
		pObj->SetReg(reg, ZD_CR11, 0x00);
		pObj->SetReg(reg, ZD_CR161, 0x28);
		pObj->SetReg(reg, ZD_CR162, 0x26);

		pObj->SetReg(reg, ZD_CR24, 0x0e);
		pObj->SetReg(reg, ZD_CR41, 0x24);
		pObj->SetReg(reg, ZD_CR159, 0x93);
		pObj->SetReg(reg, ZD_CR160, 0xfc);
		pObj->SetReg(reg, ZD_CR161, 0x20);
		pObj->SetReg(reg, ZD_CR162, 0x26);
#endif

		pObj->SetReg(reg, ZD_CR252, 0xff);
		pObj->SetReg(reg, ZD_CR253, 0xff);
                
		//UnLockPhyReg(pObj);
		
        if (pObj->rfMode == AL2230S_RF)
        {
            pObj->SetReg(reg, ZD_CR47 , 0x1E); //MARK_002 
            pObj->SetReg(reg, ZD_CR106, 0x22); 
            pObj->SetReg(reg, ZD_CR107, 0x2A); //MARK_002
            pObj->SetReg(reg, ZD_CR109, 0x13); //MARK_002           
            pObj->SetReg(reg, ZD_CR118, 0xF8); //MARK_002
            pObj->SetReg(reg, ZD_CR119, 0x12);
            pObj->SetReg(reg, ZD_CR122, 0xE0);
            pObj->SetReg(reg, ZD_CR128, 0x10); //MARK_001 from 0xe->0x10
            pObj->SetReg(reg, ZD_CR129, 0x0E); //MARK_001 from 0xd->0x0e
            pObj->SetReg(reg, ZD_CR130, 0x10); //MARK_001 from 0xb->0x0d
        }
        UnLockPhyReg(pObj);
		HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3]);
		HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3+1]);
		HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3+2]);
		HW_Set_IF_Synthesizer(pObj, 0x0b3331);
		HW_Set_IF_Synthesizer(pObj, 0x03b812);
		HW_Set_IF_Synthesizer(pObj, 0x00fff3);
        if (pObj->rfMode == AL2230S_RF)
            HW_Set_IF_Synthesizer(pObj, 0x000824);  //improve band edge for AL2230S
        else
            HW_Set_IF_Synthesizer(pObj, 0x0005a4);

		HW_Set_IF_Synthesizer(pObj, 0x000da4);
		HW_Set_IF_Synthesizer(pObj, 0x0f4dc5); // fix freq shift, 0x04edc5, 1211 is differ from 1211B
		HW_Set_IF_Synthesizer(pObj, 0x0805b6);
		HW_Set_IF_Synthesizer(pObj, 0x011687);
		HW_Set_IF_Synthesizer(pObj, 0x000688);
		HW_Set_IF_Synthesizer(pObj, 0x0403b9);   //External control TX power (CR31)
		HW_Set_IF_Synthesizer(pObj, 0x00dbba);
		HW_Set_IF_Synthesizer(pObj, 0x00099b);
		HW_Set_IF_Synthesizer(pObj, 0x0bdffc);
		HW_Set_IF_Synthesizer(pObj, 0x00000d);
		HW_Set_IF_Synthesizer(pObj, 0x00500f);

		LockPhyReg(pObj);
		pObj->SetReg(reg, ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
		pObj->SetReg(reg, ZD_CR251, 0x3f); // shdnb(PLL_ON)=1
		pObj->DelayUs(10);
		UnLockPhyReg(pObj);
		HW_Set_IF_Synthesizer(pObj, 0x000d00f);
		pObj->DelayUs(100);
		HW_Set_IF_Synthesizer(pObj, 0x0004c0f);
		pObj->DelayUs(100);
		HW_Set_IF_Synthesizer(pObj, 0x00540f);
		pObj->DelayUs(100);
		HW_Set_IF_Synthesizer(pObj, 0x00700f);
		pObj->DelayUs(100);
        HW_Set_IF_Synthesizer(pObj, 0x00500f);

	}
	else{
		HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3]);
		HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3+1]);
		HW_Set_IF_Synthesizer(pObj, AL2230TB_1211[ChannelNo*3+2]);
	}
	
    LockPhyReg(pObj);
	pObj->SetReg(reg, ZD_CR138, 0x28);
    pObj->SetReg(reg, ZD_CR203, 0x06);
    //UnLockPhyReg(pObj);
	pObj->CR203Flag = 2;
	pObj->CR31Flag = 2;
    if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
    {
        tmpvalue = pObj->GetReg(reg, E2P_PHY_REG);
        pObj->SetReg(reg, ZD_CR47, (tmpvalue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
    }       
    
    if (pObj->HWFeature & BIT_21)  //6321 for FCC regulation, enabled per HWFeature 6M band edge bit (for AL2230, AL2230S)
    {
        if (ChannelNo == 1 || ChannelNo == 11)  //MARK_003, band edge, these may depend on PCB layout
        {
            pObj->SetReg(reg, ZD_CR128, 0x12);
            pObj->SetReg(reg, ZD_CR129, 0x12);
            pObj->SetReg(reg, ZD_CR130, 0x10);
            pObj->SetReg(reg, ZD_CR47, 0x1E);
        }
        else //(ChannelNo 2 ~ 10, 12 ~ 14)
        {
            pObj->SetReg(reg, ZD_CR128, 0x14);
            pObj->SetReg(reg, ZD_CR129, 0x12);
            pObj->SetReg(reg, ZD_CR130, 0x10);
            pObj->SetReg(reg, ZD_CR47, 0x1E);
        }
    }


#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
	pObj->SetReg(reg, ZD_PE1_PE2, 3);
#endif

    UnLockPhyReg(pObj);
}
#elif defined(ZD1211B)
void
HW_Set_AL2230_RF_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
    U32       tmpvalue;
    U16      WriteAddr[256];          
    U16      WriteData[256];  
    U16      WriteIndex = 0;
    void *reg = pObj->reg;

    LockPhyReg(pObj);
    //pObj->SetReg(reg, ZD_CR240, 0x57);
    mFILL_WRITE_REGISTER(ZD_CR240, 0x57);
    mFILL_WRITE_REGISTER(ZD_CR9, 0xe0);
    if (!InitChOnly){
        //mFILL_WRITE_REGISTER(ZD_CR9,  0xe0);
        mFILL_WRITE_REGISTER(ZD_CR10, 0x89);
        mFILL_WRITE_REGISTER(ZD_CR15, 0x20);
        mFILL_WRITE_REGISTER(ZD_CR17, 0x2B);       //for newest(3rd cut) AL2230
        mFILL_WRITE_REGISTER(ZD_CR23, 0x40);
        mFILL_WRITE_REGISTER(ZD_CR24, 0x20);
        mFILL_WRITE_REGISTER(ZD_CR26, 0x93);
        mFILL_WRITE_REGISTER(ZD_CR28, 0x3e);
        mFILL_WRITE_REGISTER(ZD_CR29, 0x00);
        mFILL_WRITE_REGISTER(ZD_CR33, 0x28);   //5621
        mFILL_WRITE_REGISTER(ZD_CR34, 0x30);
        mFILL_WRITE_REGISTER(ZD_CR35, 0x3e);  //for newest(3rd cut) AL2230
        mFILL_WRITE_REGISTER(ZD_CR41, 0x24);
        mFILL_WRITE_REGISTER(ZD_CR44, 0x32);
        mFILL_WRITE_REGISTER(ZD_CR46, 0x99);  //for newest(3rd cut) AL2230  
        mFILL_WRITE_REGISTER(ZD_CR47, 0x1e);
        mFILL_WRITE_REGISTER(ZD_CR48, 0x06);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR49, 0xf9);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR51, 0x01);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR52, 0x80);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR53, 0x7e);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR65, 0x00);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR66, 0x00);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR67, 0x00);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR68, 0x00);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR69, 0x28);       //ZD1215 05.06.10
        mFILL_WRITE_REGISTER(ZD_CR79, 0x58);
        mFILL_WRITE_REGISTER(ZD_CR80, 0x30);
        mFILL_WRITE_REGISTER(ZD_CR81, 0x30);
        mFILL_WRITE_REGISTER(ZD_CR87, 0x0a);
        mFILL_WRITE_REGISTER(ZD_CR89, 0x04);
        mFILL_WRITE_REGISTER(ZD_CR91, 0x00);   //5621
        mFILL_WRITE_REGISTER(ZD_CR92, 0x0a);
        mFILL_WRITE_REGISTER(ZD_CR98, 0x8d);  //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR99, 0x00);  //5621
        mFILL_WRITE_REGISTER(ZD_CR101, 0x13);
        mFILL_WRITE_REGISTER(ZD_CR102, 0x27);
        mFILL_WRITE_REGISTER(ZD_CR106, 0x24);  //for newest(3rd cut) AL2230   
        mFILL_WRITE_REGISTER(ZD_CR107, 0x2a);
        mFILL_WRITE_REGISTER(ZD_CR109, 0x13);  //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR110, 0x1f);  //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR111, 0x1f);
        mFILL_WRITE_REGISTER(ZD_CR112, 0x1f);
        mFILL_WRITE_REGISTER(ZD_CR113, 0x27);
        mFILL_WRITE_REGISTER(ZD_CR114, 0x27);
        mFILL_WRITE_REGISTER(ZD_CR115, 0x26); //24->26 at 4902 for newest(3rd cut) AL2230   
        mFILL_WRITE_REGISTER(ZD_CR116, 0x24); 
        mFILL_WRITE_REGISTER(ZD_CR117, 0xfa); // for 1215
        mFILL_WRITE_REGISTER(ZD_CR118, 0xfa); // for 1215
        mFILL_WRITE_REGISTER(ZD_CR119, 0x10);
        mFILL_WRITE_REGISTER(ZD_CR120, 0x4f);
        mFILL_WRITE_REGISTER(ZD_CR121, 0x6c); // for 1215
        mFILL_WRITE_REGISTER(ZD_CR122, 0xfc); // E0->FC at 4902
        mFILL_WRITE_REGISTER(ZD_CR123, 0x57); //5623
        mFILL_WRITE_REGISTER(ZD_CR125, 0xad); //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR126, 0x6c); //5614
        mFILL_WRITE_REGISTER(ZD_CR127, 0x03); //4804, for 1212 new algorithm
        mFILL_WRITE_REGISTER(ZD_CR137, 0x50); //5614
        mFILL_WRITE_REGISTER(ZD_CR138, 0xa8);
        mFILL_WRITE_REGISTER(ZD_CR144, 0xac); //5621
        mFILL_WRITE_REGISTER(ZD_CR150, 0x0d);
        mFILL_WRITE_REGISTER(ZD_CR252, 0x34);
        mFILL_WRITE_REGISTER(ZD_CR253, 0x34);

        if(pObj->rfMode == AL2230S_RF)
        {
            mFILL_WRITE_REGISTER(ZD_CR47, 0x1E);
            mFILL_WRITE_REGISTER(ZD_CR106, 0x22);
            mFILL_WRITE_REGISTER(ZD_CR107, 0x2A);
            mFILL_WRITE_REGISTER(ZD_CR109, 0x13);
            mFILL_WRITE_REGISTER(ZD_CR118, 0xF8);
            mFILL_WRITE_REGISTER(ZD_CR119, 0x12);
            mFILL_WRITE_REGISTER(ZD_CR122, 0xE0);
            mFILL_WRITE_REGISTER(ZD_CR128, 0x10);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x0E);
            mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
        }
        //mFILL_WRITE_REGISTER(ZD_CR240, 0x57);
        SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3]);
        SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3+1]);
        SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3+2]);
        SET_IF_SYNTHESIZER(macp, 0x8cccd0);
        SET_IF_SYNTHESIZER(macp, 0x481dc0);
        SET_IF_SYNTHESIZER(macp, 0xcfff00);
        if(pObj->rfMode == AL2230S_RF)
        {
            SET_IF_SYNTHESIZER(macp, 0x241000);
        }
        else
        {
            SET_IF_SYNTHESIZER(macp, 0x25A000);
        }
            
        //SET_IF_SYNTHESIZER(macp, 0x25b000);  //Reg4 update for MP version
        SET_IF_SYNTHESIZER(macp, 0x25a000);  //To improve AL2230 yield, improve phase noise, 4713
        //SET_IF_SYNTHESIZER(macp, 0xa3b720);  //Reg5 update for MP version
        SET_IF_SYNTHESIZER(macp, 0xa3b2f0);  //To improve AL2230 yield, improve phase noise, 4713
        SET_IF_SYNTHESIZER(macp, 0x6da010);  //Reg6 update for MP versio 
        //SET_IF_SYNTHESIZER(macp, 0xe16880);
        SET_IF_SYNTHESIZER(macp, 0xe36280); // Modified by jxiao for Bor-Chin on 2004/08/02
        SET_IF_SYNTHESIZER(macp, 0x116000);
        //SET_IF_SYNTHESIZER(macp, 0x9de000); //register control TX power
        SET_IF_SYNTHESIZER(macp, 0x9dc020);   //External control TX power (ZD_CR31)
        SET_IF_SYNTHESIZER(macp, 0x5ddb00);  //RegA update for MP version
        SET_IF_SYNTHESIZER(macp, 0xd99000);  //RegB update for MP version 
        SET_IF_SYNTHESIZER(macp, 0x3ffbd0);  //RegC update for MP version
        SET_IF_SYNTHESIZER(macp, 0xb00000);  //RegD update for MP version
        //SET_IF_SYNTHESIZER(macp, 0xf00a00);
        SET_IF_SYNTHESIZER(macp, 0xf01a00); //improve phase noise and remove phase calibration,4713
        /*
        mFILL_WRITE_REGISTER( CR47, 0x0);
        mFILL_WRITE_REGISTER( CR251, 0x2f); // shdnb(PLL_ON)=0
        mFILL_WRITE_REGISTER( CR251, 0x3f); // shdnb(PLL_ON)=1
        mFILL_WRITE_REGISTER( RFCFG1, 0x3); // Continuous TX
        pObj->DelayUs(10);
        SET_IF_SYNTHESIZER(macp, 0xf01100);
        pObj->DelayUs(100);
        SET_IF_SYNTHESIZER(macp, 0xf01000);
        pObj->DelayUs(100);
        mFILL_WRITE_REGISTER( RFCFG1, 0x0); // stop continuous TX
        mFILL_WRITE_REGISTER( CR47, 0x18);
        */
        mFILL_WRITE_REGISTER( ZD_CR251, 0x2f); // shdnb(PLL_ON)=0
        mFILL_WRITE_REGISTER( ZD_CR251, 0x7f); // shdnb(PLL_ON)=1
        //pObj->DelayUs(10);
        //SET_IF_SYNTHESIZER(macp, 0xf00b00);
        SET_IF_SYNTHESIZER(macp, 0xf01b00); //To improve AL2230 yield, 4713
        //pObj->DelayUs(100);
        //SET_IF_SYNTHESIZER(macp, 0xf03200); //remove phase calibration, 4713
        //pObj->DelayUs(100);
        //SET_IF_SYNTHESIZER(macp, 0xf02a00);  //remove phase calibration, 4713
        //pObj->DelayUs(100);
        //SET_IF_SYNTHESIZER(macp, 0xf00e00);
        SET_IF_SYNTHESIZER(macp, 0xf01e00);  //To improve AL2230 yield, 4713
        //pObj->DelayUs(100);
        //SET_IF_SYNTHESIZER(macp, 0xf00a00);
        SET_IF_SYNTHESIZER(macp, 0xf01a00); //To improve AL2230 yield,4713
    }
    else{
        SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3]);
        SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3+1]);
        SET_IF_SYNTHESIZER(macp, AL2230TB[ChannelNo*3+2]);
    }
    //Band Edge issue
    //if(pObj->CardSetting.NetworkTypeInUse == Ndis802_11OFDM24)

        if(pObj->HWFeature & BIT_21)
        {

            if(ChannelNo == 1 || ChannelNo == 11)
            {
                if(1)//Adapter->PHY_Decrease_CR128_state)
                {
                    mFILL_WRITE_REGISTER(ZD_CR128, 0x12);
                    mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
                    mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
                }
                else
                {
                    mFILL_WRITE_REGISTER(ZD_CR128, 0x10);
                    mFILL_WRITE_REGISTER(ZD_CR129, 0x10);
                    mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
                }
            }

            else
            {
                mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
                mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
                mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
            }
        }
        else
        {
            mFILL_WRITE_REGISTER(ZD_CR128, 0x14);
            mFILL_WRITE_REGISTER(ZD_CR129, 0x12);
            mFILL_WRITE_REGISTER(ZD_CR130, 0x10);
        }


    mFILL_WRITE_REGISTER(ZD_CR80, 0x30);
    mFILL_WRITE_REGISTER(ZD_CR81, 0x30);
    mFILL_WRITE_REGISTER(ZD_CR79, 0x58);
    mFILL_WRITE_REGISTER(ZD_CR12, 0xF0);
    mFILL_WRITE_REGISTER(ZD_CR77, 0x1B);
    mFILL_WRITE_REGISTER(ZD_CR78, 0x58);
    //mFILL_WRITE_REGISTER(ZD_CR138, 0xa8);//Org:0x28//ComTrend:RalLink AP
    //if (!pObj->ZDEnterCALMode_Used) // Do not modify CR203 during CAL mode
    if(1)
    {   
        //mFILL_WRITE_REGISTER(ZD_CR138, 0xa8);//Org:0x28//ComTrend:RalLink AP
        mFILL_WRITE_REGISTER( ZD_CR203, 0x06);
    }
    ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);
    //ZD1205_READ_REGISTER(Adapter,CtlReg1, &tmpvalue);
    //pObj->SetReg(reg, ZD_CR240, 0x80);
    mFILL_WRITE_REGISTER(ZD_CR240, 0x80);
    if(pObj->PHYNEWLayout)
    {
        if (1)
        {
  	    mFILL_WRITE_REGISTER(ZD_CR9, 0xe1);
        }
        else
        {
  	    mFILL_WRITE_REGISTER(ZD_CR9, 0xe5);
        }
    }
    if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
    {
	tmpvalue = pObj->GetReg(reg, E2P_PHY_REG);
  	mFILL_WRITE_REGISTER(ZD_CR47, tmpvalue & 0xff);
    }
        //pObj->SetReg(reg, ZD_CR47, (tmpvalue & 0xff)); //This feature is OK to be overwritten with a lower value by other feature

    mFILL_WRITE_REGISTER(ZD_CR203, 0x06);
    ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex);
    UnLockPhyReg(pObj);

    pObj->CR203Flag = 2;
    //pObj->CR31Flag = cCR31InitialState;
    //Adapter->Change_SetPoint = 2;
    //Adapter->PHY_G_BandEdge_Flag = 0;

#if !( (defined(OFDM) && defined(GCCK)) || defined(ECCK_60_5) )
    pObj->SetReg(reg, PE1_PE2, 3);
    //ZD1205_WRITE_REGISTER(Adapter,PE1_PE2, 3);
#endif

}


#endif
#endif //AL2230 Support



//2-step LNA for RF2959
#if ZDCONF_RF_RFMD_SUPPORT == 1	
void
HW_Set_RFMD_Chips(zd_80211Obj_t *pObj, U32 ChannelNo, U8 InitChOnly)
{
	void *reg = pObj->reg;

	LockPhyReg(pObj);
    
	// Get Phy-Config permission
	if (!InitChOnly ){
		//LockPhyReg(pObj);
		pObj->SetReg(reg, ZD_CR2, 0x1E);
		pObj->SetReg(reg, ZD_CR9, 0x20);
		//pObj->SetReg(reg, ZD_CR10, 0xB1);
		pObj->SetReg(reg, ZD_CR10, 0x89);
		pObj->SetReg(reg, ZD_CR11, 0x00);
		pObj->SetReg(reg, ZD_CR15, 0xD0);
#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR17, 0x68);
#elif defined(ZD1211B)
		pObj->SetReg(reg, ZD_CR17, 0x2b);
#endif
		pObj->SetReg(reg, ZD_CR19, 0x4a);
		pObj->SetReg(reg, ZD_CR20, 0x0c);
		pObj->SetReg(reg, ZD_CR21, 0x0E);
		pObj->SetReg(reg, ZD_CR23, 0x48);

		if (pObj->bIsNormalSize)
			pObj->SetReg(reg, ZD_CR24, 0x14);//cca threshold
		else
			pObj->SetReg(reg, ZD_CR24, 0x20);//cca threshold

		pObj->SetReg(reg, ZD_CR26, 0x90);
		pObj->SetReg(reg, ZD_CR27, 0x30);
		pObj->SetReg(reg, ZD_CR29, 0x20);
		pObj->SetReg(reg, ZD_CR31, 0xb2);
		//pObj->SetReg(reg, ZD_CR31, 0xaa);
		pObj->SetReg(reg, ZD_CR32, 0x43);
		pObj->SetReg(reg, ZD_CR33, 0x28);
		pObj->SetReg(reg, ZD_CR38, 0x30);
		pObj->SetReg(reg, ZD_CR34, 0x0f);
		pObj->SetReg(reg, ZD_CR35, 0xF0);
		pObj->SetReg(reg, ZD_CR41, 0x2a);
		pObj->SetReg(reg, ZD_CR46, 0x7F);
		pObj->SetReg(reg, ZD_CR47, 0x1E);
#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR51, 0xc5);
		pObj->SetReg(reg, ZD_CR52, 0xc5);
		pObj->SetReg(reg, ZD_CR53, 0xc5);
#elif defined(ZD1211B)
        pObj->SetReg(reg, ZD_CR51, 0x01);
        pObj->SetReg(reg, ZD_CR52, 0x80);
        pObj->SetReg(reg, ZD_CR53, 0x7e);

		pObj->SetReg(reg,ZD_CR48, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR49, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR65, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR66, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR67, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR68, 0x00);		//ZD1211B 05.06.10
		pObj->SetReg(reg,ZD_CR69, 0x28);		//ZD1211B 05.06.10

#endif
		pObj->SetReg(reg, ZD_CR79, 0x58);
		pObj->SetReg(reg, ZD_CR80, 0x30);
		pObj->SetReg(reg, ZD_CR81, 0x30);
		pObj->SetReg(reg, ZD_CR82, 0x00);
		pObj->SetReg(reg, ZD_CR83, 0x24);
		pObj->SetReg(reg, ZD_CR84, 0x04);
		pObj->SetReg(reg, ZD_CR85, 0x00);
		pObj->SetReg(reg, ZD_CR86, 0x10);
		pObj->SetReg(reg, ZD_CR87, 0x2A);
		pObj->SetReg(reg, ZD_CR88, 0x10);
		pObj->SetReg(reg, ZD_CR89, 0x24);
		pObj->SetReg(reg, ZD_CR90, 0x18);
		//pObj->SetReg(reg, ZD_CR91, 0x18);
		pObj->SetReg(reg, ZD_CR91, 0x00); // to solve continuous CTS frames problem
		pObj->SetReg(reg, ZD_CR92, 0x0a);
		pObj->SetReg(reg, ZD_CR93, 0x00);
		pObj->SetReg(reg, ZD_CR94, 0x01);
		pObj->SetReg(reg, ZD_CR95, 0x00);
		pObj->SetReg(reg, ZD_CR96, 0x40);

		pObj->SetReg(reg, ZD_CR97, 0x37);
#ifdef HOST_IF_USB	
	#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR98, 0x05);
	#elif defined(ZD1211B)
		pObj->SetReg(reg, ZD_CR98, 0x8d);
	#endif
#else
		pObj->SetReg(reg, ZD_CR98, 0x0D);
		pObj->SetReg(reg, ZD_CR121, 0x06);
		pObj->SetReg(reg, ZD_CR125, 0xAA);
#endif
		pObj->SetReg(reg, ZD_CR99, 0x28);
		pObj->SetReg(reg, ZD_CR100, 0x00);
		pObj->SetReg(reg, ZD_CR101, 0x13);
		pObj->SetReg(reg, ZD_CR102, 0x27);
		pObj->SetReg(reg, ZD_CR103, 0x27);
		pObj->SetReg(reg, ZD_CR104, 0x18);
		pObj->SetReg(reg, ZD_CR105, 0x12);
		
		if (pObj->bIsNormalSize)

			pObj->SetReg(reg, ZD_CR106, 0x1a);
		else
			pObj->SetReg(reg, ZD_CR106, 0x22);

		pObj->SetReg(reg, ZD_CR107, 0x24);
		pObj->SetReg(reg, ZD_CR108, 0x0a);
		pObj->SetReg(reg, ZD_CR109, 0x13);
#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR110, 0x2F);
#elif defined(ZD1211B)
		pObj->SetReg(reg, ZD_CR110, 0x1F);
#endif
		pObj->SetReg(reg, ZD_CR111, 0x27);
		pObj->SetReg(reg, ZD_CR112, 0x27);
		pObj->SetReg(reg, ZD_CR113, 0x27);
		pObj->SetReg(reg, ZD_CR114, 0x27);
#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR115, 0x40);
		pObj->SetReg(reg, ZD_CR116, 0x40);
		pObj->SetReg(reg, ZD_CR117, 0xF0);
		pObj->SetReg(reg, ZD_CR118, 0xF0);
#elif defined(ZD1211B)
        pObj->SetReg(reg, ZD_CR115, 0x26);
        pObj->SetReg(reg, ZD_CR116, 0x40);
        pObj->SetReg(reg, ZD_CR117, 0xFA);
        pObj->SetReg(reg, ZD_CR118, 0xFA);
		pObj->SetReg(reg, ZD_CR121, 0x6C);
#endif
        pObj->SetReg(reg, ZD_CR119, 0x16);
		//pObj->SetReg(reg, ZD_CR122, 0xfe);
		if (pObj->bContinueTx)
			pObj->SetReg(reg, ZD_CR122, 0xff);
		else	
			pObj->SetReg(reg, ZD_CR122, 0x00);
		pObj->CR122Flag = 2;
#ifdef ZD1211B
		pObj->SetReg(reg,ZD_CR125, 0xad);  //4804, for 1212 new algorithm
		pObj->SetReg(reg,ZD_CR126, 0x6c);  //5614

#endif
		
		pObj->SetReg(reg, ZD_CR127, 0x03);
		pObj->SetReg(reg, ZD_CR131, 0x08);
		pObj->SetReg(reg, ZD_CR138, 0x28);
		pObj->SetReg(reg, ZD_CR148, 0x44);
#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR150, 0x10);
#elif defined(ZD1211B)
		pObj->SetReg(reg, ZD_CR150, 0x14);
#endif
		pObj->SetReg(reg, ZD_CR169, 0xBB);
		pObj->SetReg(reg, ZD_CR170, 0xBB);
		//pObj->SetReg(reg, ZD_CR38, 0x30);
		//UnLockPhyReg(pObj);
                                                          
		HW_Set_IF_Synthesizer(pObj, 0x000007);  //REG0(CFG1)
		HW_Set_IF_Synthesizer(pObj, 0x07dd43);  //REG1(IFPLL1)
		HW_Set_IF_Synthesizer(pObj, 0x080959);  //REG2(IFPLL2)
		HW_Set_IF_Synthesizer(pObj, 0x0e6666);
		HW_Set_IF_Synthesizer(pObj, 0x116a57);  //REG4
		HW_Set_IF_Synthesizer(pObj, 0x17dd43);  //REG5
		HW_Set_IF_Synthesizer(pObj, 0x1819f9);  //REG6
		HW_Set_IF_Synthesizer(pObj, 0x1e6666);
		HW_Set_IF_Synthesizer(pObj, 0x214554);
		HW_Set_IF_Synthesizer(pObj, 0x25e7fa);
		HW_Set_IF_Synthesizer(pObj, 0x27fffa);
		//HW_Set_IF_Synthesizer(pObj, 0x294128);  //Register control TX power
		// set in Set_RF_Channel( )
		//HW_Set_IF_Synthesizer(pObj, 0x28252c);    //External control TX power (CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M
		HW_Set_IF_Synthesizer(pObj, 0x2c0000);
		HW_Set_IF_Synthesizer(pObj, 0x300000);
		

		HW_Set_IF_Synthesizer(pObj, 0x340000);  //REG13(0xD)
		HW_Set_IF_Synthesizer(pObj, 0x381e0f);  //REG14(0xE)
		HW_Set_IF_Synthesizer(pObj, 0x6c180f);  //REG27(0x11)
	}
	else{
		//LockPhyReg(pObj);
		if (pObj->bContinueTx)
			pObj->SetReg(reg, ZD_CR122, 0xff);
		else	
			pObj->SetReg(reg, ZD_CR122, 0x00);
		//UnLockPhyReg(pObj);
		
		pObj->CR122Flag = 2;
        pObj->CR31Flag = 2;  

		HW_Set_IF_Synthesizer(pObj, RFMD2958t[ChannelNo*2]);
		HW_Set_IF_Synthesizer(pObj, RFMD2958t[ChannelNo*2+1]);

	}


    UnLockPhyReg(pObj);

	return;
}
#endif

void HW_EnableBeacon(zd_80211Obj_t *pObj, U16 BeaconInterval, U16 DtimPeriod, U8 BssType) 
{
	U32 tmpValue;
	U32 Mode = 0;
	U16 Dtim = 0;

	void *reg = pObj->reg;
	
#if ZDCONF_ADHOC_SUPPORT == 1
	if (BssType == INDEPENDENT_BSS){
		Mode = IBSS_MODE;
		printk(KERN_ERR "Mode: IBSS_MODE\n");
	}	
#endif
#if ZDCONF_AP_SUPPORT == 1
	if (BssType == AP_BSS){
		Mode = AP_MODE;
		Dtim = DtimPeriod;
		printk(KERN_ERR "Mode: AP_BSS\n");
	}	
#endif
		
	tmpValue = BeaconInterval | Mode | (Dtim<<16) ;
	pObj->SetReg(reg, ZD_BCNInterval, tmpValue);
}	


void HW_SwitchChannel(zd_80211Obj_t *pObj, U16 channel, U8 InitChOnly, const U8 MAC_Mode)
{
	void *reg = pObj->reg;


	pObj->SetReg(reg, ZD_CONFIGPhilips, 0x0);

	//FPRINT_V("rfMode", pObj->rfMode);

	switch(pObj->rfMode)
	{
		default:
			printk("Invalid RF module parameter:%u", pObj->rfMode);

			break;
/*			
		case MAXIM_NEW_RF:
			FPRINT_V("MAXIM_NEW_RF Channel", channel);
			pObj->S_bit_cnt = 18;
			HW_Set_Maxim_New_Chips(pObj, channel, 0);
            
		#ifdef HOST_IF_USB
            HW_UpdateIntegrationValue(pObj, channel, MAC_Mode);
		#endif
			break;
*/

/*
		case GCT_RF:
		//	FPRINT_V("GCT Channel", channel);
			pObj->S_bit_cnt = 21;
            
			pObj->AcquireDoNotSleep();
			if (!pObj->bDeviceInSleep)
				HW_Set_GCT_Chips(pObj, channel, InitChOnly);
			pObj->ReleaseDoNotSleep();
			//HW_UpdateIntegrationValue(pObj, channel);
			break;
*/
#if ZDCONF_RF_UW2453_SUPPORT == 1
        case UW2453_RF:
            pObj->S_bit_cnt = 24;
            HW_Set_UW2453_RF_Chips(pObj, channel, InitChOnly);
            break;
#endif
#if ZDCONF_RF_AR2124_SUPPORT == 1
        case AR2124_RF:
            pObj->S_bit_cnt = 24;
            HW_Set_AR2124_RF_Chips(pObj, channel, InitChOnly);
            break;
#endif
#if ZDCONF_RF_AL2230_SUPPORT == 1
		case AL2230_RF:
        case AL2230S_RF:
			//FPRINT_V("AL2210MPVB_RF Channel", channel);
			pObj->S_bit_cnt = 24;
			HW_Set_AL2230_RF_Chips(pObj, channel, InitChOnly);
			//HW_UpdateIntegrationValue(pObj, channel, MAC_Mode);
			break;	
#endif
#if ZDCONF_RF_AL7230B_SUPPORT == 1
		case AL7230B_RF: //For 802.11a/b/g
			FPRINT_V("AL7230B_RF",channel);
			pObj->S_bit_cnt = 24;
			HW_Set_AL7230B_RF_Chips(pObj, channel, InitChOnly,MAC_Mode);
			break;			
#endif
/*
		case AL2210_RF:	
			//FPRINT_V("AL2210_RF Channel", channel);
			pObj->S_bit_cnt = 24;
			HW_Set_AL2210_Chips(pObj, channel, 0);
			break;		
		
		case RALINK_RF:
			FPRINT_V("Ralink Channel", channel);
			break;
			
		case INTERSIL_RF:
			FPRINT_V("Intersil Channel", channel);
			break;
*/
#if ZDCONF_RF_RFMD_SUPPORT == 1	
		case RFMD_RF:
			FPRINT_V("RFMD Channel", channel);
			pObj->S_bit_cnt = 24;
			HW_Set_RFMD_Chips(pObj, channel, InitChOnly);
            

            if (!InitChOnly)
			    HW_UpdateIntegrationValue(pObj, channel, MAC_Mode);
			break;
#endif
/*			
		case MAXIM_NEW_RF2:
			FPRINT_V("MAXIM_NEW_RF2 Channel", channel);

			pObj->S_bit_cnt = 18;
			HW_Set_Maxim_New_Chips2(pObj, channel, 0);
			break;
			
		case PHILIPS_RF:
			FPRINT_V("Philips SA2400 Channel", channel);
			break;
*/
	}
	
	HW_OverWritePhyRegFromE2P(pObj);

	return;
}



void HW_SetRfChannel(zd_80211Obj_t *pObj, U16 channel, U8 InitChOnly, const U8 MAC_Mode)
{
	void *reg = pObj->reg;
	//FPRINT_V("HW_SetRfChannel", channel);
    
	// Check if this ChannelNo allowed?
	u32 i;

	if (!((1 << (channel-1)) & pObj->AllowedChannel)){
		// Not an allowed channel, we use default channel.
		//printk("Channel = %d Not an allowed channel\n", channel);
		//printk("Set default channel = %d\n", (pObj->AllowedChannel >> 16));
		//channel = (pObj->AllowedChannel >> 16);
		if(PURE_A_MODE != MAC_Mode) {
			//printk("You use a non-allowed channel in HW_setRfChannel(%d)\n",channel);
			return;
		}
	}

	//Check if channel is valid 2.4G Band
	if(MAC_Mode != PURE_A_MODE) {
		if ((channel > 14 ) || (channel < 1)){ // for the wrong content of the EEPROM
			printk(KERN_DEBUG "Error Channel Number in HW_SetRfChannel(11b/g)\n");
			return;
		}
	}
#if ZDCONF_80211A_SUPPORT == 1
	else if(MAC_Mode == PURE_A_MODE) {
		//Check is the A Band Channel is valid.
		for(i=0;i<dot11A_Channel_Amount;i++)
			if(dot11A_Channel[i] == channel)
				break;
		if(i>=dot11A_Channel_Amount) {
			printk(KERN_DEBUG "Error Channel Number in HW_SetRfChannel(11a,CH=%d)\n",channel);
			return;
		}
	}
	if(PURE_A_MODE == MAC_Mode) {
		pObj->SetReg(pObj->reg, ZD_IFS_Value, 0x0a47c00a);
		pObj->SetReg(pObj->reg, ZD_RTS_CTS_Rate, 0x01090109);
	}
	else 
#endif
    {
		pObj->SetReg(pObj->reg, ZD_IFS_Value, 0xa47c032);
		pObj->SetReg(pObj->reg, ZD_RTS_CTS_Rate, 0x30000);
	}

	pObj->Channel = channel;
	HW_SwitchChannel(pObj, channel, InitChOnly,MAC_Mode);
	LastSetChannel = channel;
	LastMacMode = MAC_Mode;

	//The UpdateIntegrationValue call should be called immediately 
	//after HW_SetRfChannel
    if(pObj->bChScanning == 0)
        HW_UpdateIntegrationValue(pObj, channel,MAC_Mode);
	
	// When channnel == 14 , enable Japan spectrum mask
	if (pObj->RegionCode == 0x40) { //Japan
		if (channel == 14){
			HW_Set_FilterBand(pObj, pObj->RegionCode);  // for Japan, RegionCode = 0x40
#if ZDCONF_RF_RFMD_SUPPORT == 1	
			if (pObj->rfMode == RFMD_RF){
				LockPhyReg(pObj);
				pObj->SetReg(reg, ZD_CR47, 0x1E);
				//UnLockPhyReg(pObj);

				HW_Set_IF_Synthesizer(pObj, 0x28252d);    //External control TX power (CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M
                UnLockPhyReg(pObj);
			}
#endif

		}
		else{

			// For other channels, use default filter.
			HW_Set_FilterBand(pObj, 0); 
						
			if (pObj->rfMode == RFMD_RF){
				// CR47 has been restored in Init_RF_Chips( ), its value is from EEPROM
				HW_Set_IF_Synthesizer(pObj, 0x28252d);    //External control TX power (CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M
			}
		}
	} 
	
	pObj->DelayUs(100);
}

void HW_SetBeaconFIFO(zd_80211Obj_t *pObj, U8 *pBeacon, U16 index)
{
	U32 tmpValue=0xdeadbeef, BCNPlcp=0xdeadbeef;
	U16 j;
	void *reg = pObj->reg;
	U32 count = 1;
    U16      *WriteAddr;
    U16      *WriteData;
    U16 WriteIndex=0;

	//pObj->SetReg(reg, ZD_BCN_FIFO_Semaphore, 0x0);
	//tmpValue = pObj->GetReg(reg, ZD_BCN_FIFO_Semaphore); //FIXME. Should be uncomment !?
    //Declare Write* as array may cause stack overflow
    WriteAddr = kmalloc(256*sizeof(U16), GFP_KERNEL); 
    WriteData = kmalloc(256*sizeof(U16), GFP_KERNEL);
    if(WriteAddr == NULL || WriteData == NULL)
    {
        printk("OOM occur in %s\n", __func__);
        return;
    }

    if(WriteAddr == NULL || WriteData == NULL)
    {
        printk("OOM occur in %s\n", __func__);
        return;
    }

	while (tmpValue & BIT_1){
		pObj->DelayUs(1000);
		tmpValue = pObj->GetReg(reg, ZD_BCN_FIFO_Semaphore);
		
		if ((++count % 100) == 0)
			printk(KERN_ERR "Get ZD_BCN_FIFO_Semaphore not ready\n");
	}
	
	pObj->SetReg(reg, ZD_BCN_FIFO_Semaphore, 0x0);
	tmpValue = pObj->GetReg(reg, ZD_BCN_FIFO_Semaphore);
	/* Write (Beacon_Len -1) to Beacon-FIFO */
	pObj->SetReg(reg, ZD_BCNFIFO, (index - 1));
#ifdef ZD1211B
	pObj->SetReg(reg,ZD_BCNLENGTH, (index - 1));
#endif

	for (j=0; j<index; j++){
        mFILL_WRITE_REGISTER(ZD_BCNFIFO, pBeacon[j]);
		//pObj->SetReg(reg, ZD_BCNFIFO, pBeacon[j]);	
	}
    ZD1211_WRITE_MULTI_REG(WriteAddr, WriteData, &WriteIndex); 
	pObj->SetReg(reg, ZD_BCN_FIFO_Semaphore, 1);	
	
	/* Configure BCNPLCP */
    if(mMacMode == PURE_A_MODE)  {
        BCNPlcp = 0x0000003b; //802.11a 5g OFDM 6Mb
    }
    else
    {
        index = (index << 3); //802.11b/g 2.4G CCK 1Mb
        BCNPlcp = 0x00000400;
    }
	BCNPlcp |= (((U32)index) << 16);
	pObj->SetReg(reg, ZD_BCNPLCPCfg, BCNPlcp);
    kfree(WriteAddr);
    kfree(WriteData);

}



void HW_SetSupportedRate(zd_80211Obj_t *pObj, U8 *prates)
{
	U8 HighestBasicRate = SR_1M;
	U8 HighestRate = SR_1M;
	U8 SRate;
	U32 tmpValue;
	U16 j;
	U8 MaxBasicRate;
	
	void *reg = pObj->reg;	
	MaxBasicRate = pObj->BasicRate; 
	

	for (j=0; j<(*(prates+1)); j++){
		switch((*(prates+2+j)) & 0x7f){
			case SR_1M:
				SRate = SR_1M;
#if defined(AMAC)				
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate

					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_0;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
#endif				
				break;
				
			case SR_2M:
				SRate = SR_2M;
#if defined(AMAC)				
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_1;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
#endif				
				break;
				
			case SR_5_5M:
				SRate = SR_5_5M;
#if defined(AMAC)				
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);

					tmpValue |= BIT_2;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
#endif					
				break;
				
			case SR_11M:
				SRate = SR_11M;
#if defined(AMAC)				
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_3;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}

#endif				
				break;

#if	(defined(GCCK) && defined(OFDM))
			case SR_6M:
				SRate = SR_6M;
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_8;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
				break;
				
			case SR_9M:
				SRate = SR_9M;
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_9;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
				break;
				
			case SR_12M:
				SRate = SR_12M;
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_10;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
				break;
				
			case SR_18M:
				SRate = SR_18M;
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_11;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
				break;
				
			case SR_24M:
				SRate = SR_24M;
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_12;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
				break;
				
			case SR_36M:
				SRate = SR_36M;
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_13;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);

				}
				break;
				
			case SR_48M:
				SRate = SR_48M;
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_14;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
				break;
				
			case SR_54M:
				SRate = SR_54M;
				if ((*(prates+2+j)) & 0x80){	//It's a basic rate
					tmpValue = pObj->GetReg(reg, ZD_BasicRateTbl);
					tmpValue |= BIT_15;
					pObj->SetReg(reg, ZD_BasicRateTbl, tmpValue);
				}
				break;
#endif
				
			default:
				SRate = SR_1M;

				break;
		}

		if (HighestRate < SRate)
			HighestRate = SRate;


		if ((*(prates+2+j)) & 0x80){
		/* It's a basic rate */
			if (HighestBasicRate < SRate)
				HighestBasicRate = SRate;
		}
	}

#if !defined(OFDM)
	tmpValue = pObj->GetReg(reg, ZD_CtlReg1);
	
#if ZDCONF_ADHOC_SUPPORT == 1
	if (pObj->BssType == INDEPENDENT_BSS){
		if (HighestBasicRate == SR_1M){
			// Workaround compatibility issue.
			// For resonable case, HighestBasicRate should larger than 2M if

			// short-preamble is supported.
			HighestBasicRate = SR_2M;
			pObj->SetReg(reg, ZD_Ack_Timeout_Ext, 0x3f);
		}
	}
#endif
	
	switch(HighestBasicRate){
		case SR_1M:
			tmpValue &= ~0x1c;
			tmpValue |= 0x00;
			pObj->SetReg(reg, ZD_CtlReg1, tmpValue);
			pObj->BasicRate = 0x0;
			break;
			
		case SR_2M:
			tmpValue &= ~0x1c;
			tmpValue |= 0x04; 
			pObj->SetReg(reg, ZD_CtlReg1, tmpValue);
			pObj->BasicRate = 0x1;
			break;
			
		case SR_5_5M:
			tmpValue &= ~0x1c;

			tmpValue |= 0x08;
			pObj->SetReg(reg, ZD_CtlReg1, tmpValue);
			pObj->BasicRate = 0x2;
			break;
			
		case SR_11M:
			tmpValue &= ~0x1c;
			tmpValue |= 0x0c;
			pObj->SetReg(reg, ZD_CtlReg1, tmpValue);
			pObj->BasicRate = 0x3;
			break;
			
		default:
			break;
	}
#else
	switch(HighestBasicRate){
		case SR_1M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x0;
			break;
			

		case SR_2M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x1;
			break;
			
		case SR_5_5M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x2;
			break;
			
		case SR_11M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x3;
			break;
		
		case SR_6M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x4;
			break;
		
		case SR_9M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x5;
			break;
		
		case SR_12M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x6;
			break;
		
		case SR_18M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x7;
			break;
		
		case SR_24M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x8;
			break;
		
		case SR_36M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0x9;
			break;
		
		case SR_48M:
			if (HighestBasicRate >= MaxBasicRate)

				pObj->BasicRate = 0xa;
			break;
			
		case SR_54M:
			if (HighestBasicRate >= MaxBasicRate)
				pObj->BasicRate = 0xb;
			break;	
										
		default:

			break;
	}
#endif

	//FPRINT_V("HighestBasicRate", pObj->BasicRate);
}		

extern U16 mBeaconPeriod;

void HW_SetSTA_PS(zd_80211Obj_t *pObj, U8 op)
{
#if 0
	void *reg = pObj->reg;
	U32 tmpValue;
	
	tmpValue = pObj->GetReg(reg, ZD_BCNInterval);

	/* Beacon interval check */
	if((tmpValue & 0xffff) != mBeaconPeriod) {
		printk(KERN_ERR "Beacon Interval not match\n");
        printk("tmpvalue=%08x,mBeaconPeriod=%08x\n", tmpValue, mBeaconPeriod);
		return ;
	}
    //printk(KERN_DEBUG "SetSTA_PS:%d\n",HW_GetNow(pObj));
	//if (op)
	//	tmpValue |= STA_PS;
	//else
		tmpValue &= ~STA_PS;	
	
	pObj->SetReg(reg, ZD_BCNInterval, tmpValue);
#endif
}


void HW_GetTsf(zd_80211Obj_t *pObj, U32 *loTsf, U32 *hiTsf)
{
	void *reg = pObj->reg;
	

	*loTsf = pObj->GetReg(reg, ZD_TSF_LowPart);
	*hiTsf = pObj->GetReg(reg, ZD_TSF_HighPart);
}		

U32 HW_GetNow(zd_80211Obj_t *pObj)
{
#ifndef HOST_IF_USB	
	void *reg = pObj->reg;
	return pObj->GetReg(reg, ZD_TSF_LowPart);  //us unit
#else
	return jiffies; //10ms unit
#endif    
}	

void HW_RadioOnOff(zd_80211Obj_t *pObj, U8 on)
{
	void *reg = pObj->reg;
	U32	tmpvalue;
	U8 ii;


	if (on){
		//++ Turn on RF
		switch(pObj->rfMode){
#if ZDCONF_RF_RFMD_SUPPORT == 1	
			case RFMD_RF:
            	if (!(pObj->PhyTest & BIT_2))
                	HW_Set_IF_Synthesizer(pObj, 0x000007);
                	
            	if (!(pObj->PhyTest & BIT_0)){
                	LockPhyReg(pObj);
 					pObj->SetReg(reg, ZD_CR10, 0x89);

					pObj->SetReg(reg, ZD_CR11, 0x00);
                	tmpvalue = pObj->GetReg(reg, ZD_CR11);
                	tmpvalue &= 0xFF;
                	if (tmpvalue != 0x00) {
                    	if (pObj->PhyTest & BIT_1) {
                        	for (ii = 0; ii < 10; ii ++){
                            	pObj->DelayUs(1000);
                            	pObj->SetReg(reg, ZD_CR11, 0x00);
                           		tmpvalue = pObj->GetReg(reg, ZD_CR11);
                            	if ((tmpvalue & 0xFF) == 0x00)
                                	break;
                        	}
                    	}
                 	}
                	
                	UnLockPhyReg(pObj);
            	}
            	break;
#endif
            case UW2453_RF:
            case AR2124_RF:
            case AL2230_RF:
            case AL2230S_RF:
            case AL7230B_RF:	

                if(UW2453_RF == pObj->rfMode || AR2124_RF == pObj->rfMode)
                {
                    HW_Set_IF_Synthesizer(pObj, 0x025f94); 
                    printk(KERN_DEBUG "RadioOn\n");
                }

                LockPhyReg(pObj);
                //tmpvalue &= 0xFF; // marked to remove Compiler Warning.

                for (ii = 0; ii < 10; ii ++){
                        pObj->DelayUs(1000);
                        pObj->SetReg(reg, ZD_CR11, 0x00);
                        tmpvalue = pObj->GetReg(reg, ZD_CR11);
                        if ((tmpvalue & 0xFF) == 0x00)
                                break;
                }
#ifdef ZD1211 
                pObj->SetReg(reg, ZD_CR251, 0x3f); 
#elif defined(ZD1211B)
                pObj->SetReg(reg, ZD_CR251, 0x7f);
#else
#error "You do not define ZD1211 Model"
#endif
                UnLockPhyReg(pObj);
            	break;  
        

			default:
				break;	
		}		
	}
	else{
		//++ Turn off RF
		switch(pObj->rfMode){
#if ZDCONF_RF_RFMD_SUPPORT == 1	
			case RFMD_RF:
            	if (!(pObj->PhyTest & BIT_0)){
	                LockPhyReg(pObj);

                	pObj->SetReg(reg, ZD_CR11, 0x15);
                	tmpvalue = pObj->GetReg(reg, ZD_CR11);
                	pObj->SetReg(reg, ZD_CR10, 0x81);
                	UnLockPhyReg(pObj);
                	tmpvalue &= 0xFF;
            	}
            	
            	if (!(pObj->PhyTest & BIT_2)){
                    LockPhyReg(pObj);
                	HW_Set_IF_Synthesizer(pObj, 0x00000F);
                    UnLockPhyReg(pObj);
                } 
            	break;
#endif
            case UW2453_RF:
            case AR2124_RF:
        	case AL2230_RF:
            case AL2230S_RF:
            case AL7230B_RF:	
                if(UW2453_RF == pObj->rfMode || AR2124_RF == pObj->rfMode)
                {
                    HW_Set_IF_Synthesizer(pObj, 0x025f90); 
                    printk(KERN_DEBUG "RadioOff\n");
                }
                LockPhyReg(pObj);
                pObj->SetReg(reg, ZD_CR11, 0x04);
				pObj->SetReg(reg, ZD_CR251, 0x2f); 
                UnLockPhyReg(pObj);
	            break;  
   
		
			default:
				break;		
		}		
			
	}

}	

#ifdef ZD1211 
void HW_ResetPhy(zd_80211Obj_t *pObj)
{
	void *reg = pObj->reg;
    U32 phyOverwrite;


	LockPhyReg(pObj);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR0, 0x0a);
#elif defined(ZD1211B)
	pObj->SetReg(reg, ZD_CR0, 0x14);
#endif

	pObj->SetReg(reg, ZD_CR1, 0x06);
	pObj->SetReg(reg, ZD_CR2, 0x26);
	pObj->SetReg(reg, ZD_CR3, 0x38);
	pObj->SetReg(reg, ZD_CR4, 0x80);
	pObj->SetReg(reg, ZD_CR9, 0xa0);
	pObj->SetReg(reg, ZD_CR10, 0x81);
#if fTX_PWR_CTRL && fTX_GAIN_OFDM
    //tmpvalue = pObj->GetReg(reg, ZD_CR11);
    //tmpvalue |= BIT_6;
    //pObj->SetReg(reg, ZD_CR11, tmpvalue);
    pObj->SetReg(reg, ZD_CR11, BIT_6);
#else
	pObj->SetReg(reg, ZD_CR11, 0x00);
#endif
	
	pObj->SetReg(reg, ZD_CR12, 0x7f);
	pObj->SetReg(reg, ZD_CR13, 0x8c);
	pObj->SetReg(reg, ZD_CR14, 0x80);
	pObj->SetReg(reg, ZD_CR15, 0x3d);
	pObj->SetReg(reg, ZD_CR16, 0x20);
	pObj->SetReg(reg, ZD_CR17, 0x1e);
	pObj->SetReg(reg, ZD_CR18, 0x0a);
	pObj->SetReg(reg, ZD_CR19, 0x48);
	pObj->SetReg(reg, ZD_CR20, 0x0c);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR21, 0x0c);
#elif defined(ZD1211B)
	pObj->SetReg(reg, ZD_CR21, 0x0e);
#endif
	pObj->SetReg(reg, ZD_CR22, 0x23);
	pObj->SetReg(reg, ZD_CR23, 0x90);
	pObj->SetReg(reg, ZD_CR24, 0x14);
	pObj->SetReg(reg, ZD_CR25, 0x40);
	pObj->SetReg(reg, ZD_CR26, 0x10);
	pObj->SetReg(reg, ZD_CR27, 0x19);
	pObj->SetReg(reg, ZD_CR28, 0x7f);
	pObj->SetReg(reg, ZD_CR29, 0x80);

#ifndef ASIC	

	pObj->SetReg(reg, ZD_CR30, 0x4b);
#else
	pObj->SetReg(reg, ZD_CR30, 0x49);
#endif

	pObj->SetReg(reg, ZD_CR31, 0x60);
	pObj->SetReg(reg, ZD_CR32, 0x43);
	pObj->SetReg(reg, ZD_CR33, 0x08);
	pObj->SetReg(reg, ZD_CR34, 0x06);
	pObj->SetReg(reg, ZD_CR35, 0x0a);
	pObj->SetReg(reg, ZD_CR36, 0x00);
	pObj->SetReg(reg, ZD_CR37, 0x00);
	pObj->SetReg(reg, ZD_CR38, 0x38);
	pObj->SetReg(reg, ZD_CR39, 0x0c);
	pObj->SetReg(reg, ZD_CR40, 0x84);
	pObj->SetReg(reg, ZD_CR41, 0x2a);
	pObj->SetReg(reg, ZD_CR42, 0x80);
	pObj->SetReg(reg, ZD_CR43, 0x10);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR44, 0x12);
#elif defined(ZD1211B)
	pObj->SetReg(reg, ZD_CR44, 0x33);
#endif
	
	pObj->SetReg(reg, ZD_CR46, 0xff);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR47, 0x1E);
#elif defined(ZD1211B)
	pObj->SetReg(reg, ZD_CR47, 0x1E);
#endif
	pObj->SetReg(reg, ZD_CR48, 0x26);
	pObj->SetReg(reg, ZD_CR49, 0x5b);
	

	pObj->SetReg(reg, ZD_CR64, 0xd0);
	pObj->SetReg(reg, ZD_CR65, 0x04);
	pObj->SetReg(reg, ZD_CR66, 0x58);
	pObj->SetReg(reg, ZD_CR67, 0xc9);
	pObj->SetReg(reg, ZD_CR68, 0x88);
	pObj->SetReg(reg, ZD_CR69, 0x41);
	pObj->SetReg(reg, ZD_CR70, 0x23);
	pObj->SetReg(reg, ZD_CR71, 0x10);
	pObj->SetReg(reg, ZD_CR72, 0xff);
	pObj->SetReg(reg, ZD_CR73, 0x32);
	pObj->SetReg(reg, ZD_CR74, 0x30);
	pObj->SetReg(reg, ZD_CR75, 0x65);

	pObj->SetReg(reg, ZD_CR76, 0x41);
	pObj->SetReg(reg, ZD_CR77, 0x1b);
	pObj->SetReg(reg, ZD_CR78, 0x30);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR79, 0x68);
#elif defined(ZD1211B)
	pObj->SetReg(reg, ZD_CR79, 0xf0);
#endif
	pObj->SetReg(reg, ZD_CR80, 0x64);
	pObj->SetReg(reg, ZD_CR81, 0x64);
	pObj->SetReg(reg, ZD_CR82, 0x00);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR83, 0x00);
	pObj->SetReg(reg, ZD_CR84, 0x00);
	pObj->SetReg(reg, ZD_CR85, 0x02);
	pObj->SetReg(reg, ZD_CR86, 0x00);
	pObj->SetReg(reg, ZD_CR87, 0x00);
	pObj->SetReg(reg, ZD_CR88, 0xff);
	pObj->SetReg(reg, ZD_CR89, 0xfc);
	pObj->SetReg(reg, ZD_CR90, 0x00);
	pObj->SetReg(reg, ZD_CR91, 0x00);
#elif defined(ZD1211B)
    pObj->SetReg(reg, ZD_CR83, 0x24);
    pObj->SetReg(reg, ZD_CR84, 0x04);
    pObj->SetReg(reg, ZD_CR85, 0x00);
    pObj->SetReg(reg, ZD_CR86, 0x0c);
    pObj->SetReg(reg, ZD_CR87, 0x12);
    pObj->SetReg(reg, ZD_CR88, 0x0c);
    pObj->SetReg(reg, ZD_CR89, 0x00);
    pObj->SetReg(reg, ZD_CR90, 0x58);
    pObj->SetReg(reg, ZD_CR91, 0x04);
#endif


	pObj->SetReg(reg, ZD_CR92, 0x00);
	pObj->SetReg(reg, ZD_CR93, 0x08);
	pObj->SetReg(reg, ZD_CR94, 0x00);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR95, 0x00);
#elif defined(ZD1211B)
	pObj->SetReg(reg, ZD_CR95, 0x20);
#endif
	pObj->SetReg(reg, ZD_CR96, 0xff);
	pObj->SetReg(reg, ZD_CR97, 0xe7);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR98, 0x00);
#elif defined(ZD1211B)
	pObj->SetReg(reg, ZD_CR98, 0x35);
#endif
	pObj->SetReg(reg, ZD_CR99, 0x00);
	pObj->SetReg(reg, ZD_CR100, 0x00);
	pObj->SetReg(reg, ZD_CR101, 0xae);
	pObj->SetReg(reg, ZD_CR102, 0x02);
	pObj->SetReg(reg, ZD_CR103, 0x00);
	pObj->SetReg(reg, ZD_CR104, 0x03);
	pObj->SetReg(reg, ZD_CR105, 0x65);
	pObj->SetReg(reg, ZD_CR106, 0x04);
	pObj->SetReg(reg, ZD_CR107, 0x00);
	pObj->SetReg(reg, ZD_CR108, 0x0a);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR109, 0xaa);
	pObj->SetReg(reg, ZD_CR110, 0xaa);
	pObj->SetReg(reg, ZD_CR111, 0x25);
	pObj->SetReg(reg, ZD_CR112, 0x25);
	pObj->SetReg(reg, ZD_CR113, 0x00);
	
	pObj->SetReg(reg, ZD_CR119, 0x1e);
	
	pObj->SetReg(reg, ZD_CR125, 0x90);
	pObj->SetReg(reg, ZD_CR126, 0x00);
	pObj->SetReg(reg, ZD_CR127, 0x00);
#elif defined(ZD1211B)
	pObj->SetReg(reg,ZD_CR109, 0x27);
	pObj->SetReg(reg,ZD_CR110, 0x27);
	pObj->SetReg(reg,ZD_CR111, 0x27);
	pObj->SetReg(reg,ZD_CR112, 0x27);
	pObj->SetReg(reg,ZD_CR113, 0x27);
	pObj->SetReg(reg,ZD_CR114, 0x27);
	pObj->SetReg(reg,ZD_CR115, 0x26);
	pObj->SetReg(reg,ZD_CR116, 0x24);
	pObj->SetReg(reg,ZD_CR117, 0xfc);
	pObj->SetReg(reg,ZD_CR118, 0xfa);
	pObj->SetReg(reg,ZD_CR119, 0x1e);
	pObj->SetReg(reg,ZD_CR125, 0x90);
	pObj->SetReg(reg,ZD_CR126, 0x00);
	pObj->SetReg(reg,ZD_CR127, 0x00);
	pObj->SetReg(reg,ZD_CR128, 0x14);
	pObj->SetReg(reg,ZD_CR129, 0x12);
	pObj->SetReg(reg,ZD_CR130, 0x10);
	pObj->SetReg(reg,ZD_CR131, 0x0c);
	pObj->SetReg(reg,ZD_CR136, 0xdf);
	pObj->SetReg(reg,ZD_CR137, 0xa0);
	pObj->SetReg(reg,ZD_CR138, 0xa8);
	pObj->SetReg(reg,ZD_CR139, 0xb4);
#endif


#if (defined(GCCK) && defined(OFDM))
	#ifdef ZD1211
		pObj->SetReg(reg, ZD_CR5, 0x00);
		pObj->SetReg(reg, ZD_CR6, 0x00);
		pObj->SetReg(reg, ZD_CR7, 0x00);
		pObj->SetReg(reg, ZD_CR8, 0x00);
	#endif
	pObj->SetReg(reg, ZD_CR9, 0x20);
	pObj->SetReg(reg, ZD_CR12, 0xf0);
	pObj->SetReg(reg, ZD_CR20, 0x0e);
	pObj->SetReg(reg, ZD_CR21, 0x0e);
	pObj->SetReg(reg, ZD_CR27, 0x10);
	#ifdef HOST_IF_USB	
		pObj->SetReg(reg, ZD_CR44, 0x33);
	#else	
		pObj->SetReg(reg, ZD_CR44, 0x33);
	#endif	
	pObj->SetReg(reg, ZD_CR47, 0x1E);
	pObj->SetReg(reg, ZD_CR83, 0x24);
	pObj->SetReg(reg, ZD_CR84, 0x04);
	pObj->SetReg(reg, ZD_CR85, 0x00);
	pObj->SetReg(reg, ZD_CR86, 0x0C);
	pObj->SetReg(reg, ZD_CR87, 0x12);
	pObj->SetReg(reg, ZD_CR88, 0x0C);
	pObj->SetReg(reg, ZD_CR89, 0x00);
	pObj->SetReg(reg, ZD_CR90, 0x10);
	pObj->SetReg(reg, ZD_CR91, 0x08);
	pObj->SetReg(reg, ZD_CR93, 0x00);

	pObj->SetReg(reg, ZD_CR94, 0x01);
	#ifdef HOST_IF_USB	
		pObj->SetReg(reg, ZD_CR95, 0x0); 
	#else	

	pObj->SetReg(reg, ZD_CR95, 0x20); //3d24


#endif	
	pObj->SetReg(reg, ZD_CR96, 0x50);
	pObj->SetReg(reg, ZD_CR97, 0x37);
#ifdef HOST_IF_USB	
	pObj->SetReg(reg, ZD_CR98, 0x35);
#else	
	pObj->SetReg(reg, ZD_CR98, 0x8d); //4326
#endif	
	pObj->SetReg(reg, ZD_CR101, 0x13);
	pObj->SetReg(reg, ZD_CR102, 0x27);
	pObj->SetReg(reg, ZD_CR103, 0x27);
	pObj->SetReg(reg, ZD_CR104, 0x18);
	pObj->SetReg(reg, ZD_CR105, 0x12);
	pObj->SetReg(reg, ZD_CR109, 0x27);
	pObj->SetReg(reg, ZD_CR110, 0x27);
	pObj->SetReg(reg, ZD_CR111, 0x27);
	pObj->SetReg(reg, ZD_CR112, 0x27);
	pObj->SetReg(reg, ZD_CR113, 0x27);
	pObj->SetReg(reg, ZD_CR114, 0x27);

	pObj->SetReg(reg, ZD_CR115, 0x26);
	pObj->SetReg(reg, ZD_CR116, 0x24);

	pObj->SetReg(reg, ZD_CR117, 0xfc);
	pObj->SetReg(reg, ZD_CR118, 0xfa);
	pObj->SetReg(reg, ZD_CR120, 0x4f); //3d24
#ifndef HOST_IF_USB		
	pObj->SetReg(reg, ZD_CR123, 0x27); //3d24
#endif	
	pObj->SetReg(reg, ZD_CR125, 0xaa); //4326
	pObj->SetReg(reg, ZD_CR127, 0x03); //4326
	pObj->SetReg(reg, ZD_CR128, 0x14);
	pObj->SetReg(reg, ZD_CR129, 0x12);
	pObj->SetReg(reg, ZD_CR130, 0x10);
	pObj->SetReg(reg, ZD_CR131, 0x0C);
	pObj->SetReg(reg, ZD_CR136, 0xdf);
	pObj->SetReg(reg, ZD_CR137, 0x40);
	pObj->SetReg(reg, ZD_CR138, 0xa0);
	pObj->SetReg(reg, ZD_CR139, 0xb0);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR140, 0x99);
#elif defined(ZD1211B)
	pObj->SetReg(reg, ZD_CR140, 0x98); //4407
#endif	
	pObj->SetReg(reg, ZD_CR141, 0x82);
#ifdef ZD1211
	pObj->SetReg(reg, ZD_CR142, 0x54);
#elif defined(ZD1211B)	
	pObj->SetReg(reg, ZD_CR142, 0x53); //4407
#endif	
	pObj->SetReg(reg, ZD_CR143, 0x1c);
	pObj->SetReg(reg, ZD_CR144, 0x6c);
	pObj->SetReg(reg, ZD_CR147, 0x07);
	pObj->SetReg(reg, ZD_CR148, 0x4c);
	pObj->SetReg(reg, ZD_CR149, 0x50);
	pObj->SetReg(reg, ZD_CR150, 0x0e);
	pObj->SetReg(reg, ZD_CR151, 0x18);
#ifdef ZD1211B
	pObj->SetReg(reg, ZD_CR159, 0x70); //3d24
#endif	
	pObj->SetReg(reg, ZD_CR160, 0xfe);
	pObj->SetReg(reg, ZD_CR161, 0xee);
	pObj->SetReg(reg, ZD_CR162, 0xaa);
	pObj->SetReg(reg, ZD_CR163, 0xfa);
	pObj->SetReg(reg, ZD_CR164, 0xfa);

	pObj->SetReg(reg, ZD_CR165, 0xea);
	pObj->SetReg(reg, ZD_CR166, 0xbe);
	pObj->SetReg(reg, ZD_CR167, 0xbe);
	pObj->SetReg(reg, ZD_CR168, 0x6a);
	pObj->SetReg(reg, ZD_CR169, 0xba);
	pObj->SetReg(reg, ZD_CR170, 0xba);
	pObj->SetReg(reg, ZD_CR171, 0xba);
	// Note: CR204 must lead the CR203
	pObj->SetReg(reg, ZD_CR204, 0x7d);
	pObj->SetReg(reg, ZD_CR203, 0x30);
#ifndef HOST_IF_USB	
	pObj->SetReg(reg, ZD_CR240, 0x80);
#endif
	
#endif
    //if (pObj->ChipVer == ZD_1211)
    {
        if (pObj->HWFeature & BIT_13) //6321 Bin 4 Tx IQ balance for ZD1212 only
        {
            phyOverwrite = pObj->GetReg(reg, E2P_PHY_REG);  
            printk("Overwrite CR157 = 0x%X\n", phyOverwrite); 
            pObj->SetReg(reg, ZD_CR157, ((phyOverwrite >> 8) & 0xff)); //make sure no one will overwrite CR157 again
        }
    }
    if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
    {
        phyOverwrite = pObj->GetReg(reg, E2P_PHY_REG);
        printk("Overwrite CR47 = 0x%X\n", phyOverwrite); 
        pObj->SetReg(reg, ZD_CR47, (phyOverwrite & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
    }



	UnLockPhyReg(pObj);
	return;
}	
#elif defined(ZD1211B)
void HW_ResetPhy(zd_80211Obj_t *pObj)
{
    void *reg = pObj->reg;
	u32	tmpvalue;
    U32 phyOverwrite;
    int i;

	// Get Phy-Config permission
    U8 RegVal[] = 
{
	 ZD_CR0/4, 0x14
	,ZD_CR1/4, 0x06
	,ZD_CR2/4, 0x26
	,ZD_CR3/4, 0x38
	,ZD_CR4/4, 0x80
	,ZD_CR9/4, 0xe0
	,ZD_CR10/4, 0x81
	//``JWEI 2003/12/26
#if fTX_PWR_CTRL && fTX_GAIN_OFDM
	,ZD_CR11/4, BIT_6
#else
	,ZD_CR11/4, 0x00
#endif
	,ZD_CR12/4, 0xf0
	,ZD_CR13/4, 0x8c
	,ZD_CR14/4, 0x80
	,ZD_CR15/4, 0x3d
	,ZD_CR16/4, 0x20
	,ZD_CR17/4, 0x1e
	,ZD_CR18/4, 0x0a
	,ZD_CR19/4, 0x48
	,ZD_CR20/4, 0x10//Org:0x0E,ComTrend:RalLink AP
	,ZD_CR21/4, 0x0e
	,ZD_CR22/4, 0x23
	,ZD_CR23/4, 0x90
	,ZD_CR24/4, 0x14
	,ZD_CR25/4, 0x40
	,ZD_CR26/4, 0x10
	,ZD_CR27/4, 0x10
	,ZD_CR28/4, 0x7f
	,ZD_CR29/4, 0x80
	,ZD_CR30/4, 0x4b
	,ZD_CR31/4, 0x60
	,ZD_CR32/4, 0x43
	,ZD_CR33/4, 0x08
	,ZD_CR34/4, 0x06
	,ZD_CR35/4, 0x0a
	,ZD_CR36/4, 0x00
	,ZD_CR37/4, 0x00
	,ZD_CR38/4, 0x38
	,ZD_CR39/4, 0x0c
	,ZD_CR40/4, 0x84
	,ZD_CR41/4, 0x2a
	,ZD_CR42/4, 0x80
	,ZD_CR43/4, 0x10
	,ZD_CR44/4, 0x33
	,ZD_CR46/4, 0xff
	,ZD_CR47/4, 0x1E
	,ZD_CR48/4, 0x26
	,ZD_CR49/4, 0x5b
	,ZD_CR64/4, 0xd0
	,ZD_CR65/4, 0x04
	,ZD_CR66/4, 0x58
	,ZD_CR67/4, 0xc9
	,ZD_CR68/4, 0x88
	,ZD_CR69/4, 0x41
	,ZD_CR70/4, 0x23
	,ZD_CR71/4, 0x10
	,ZD_CR72/4, 0xff
	,ZD_CR73/4, 0x32
	,ZD_CR74/4, 0x30
	,ZD_CR75/4, 0x65
	,ZD_CR76/4, 0x41
	,ZD_CR77/4, 0x1b
	,ZD_CR78/4, 0x30
	,ZD_CR79/4, 0xf0
	,ZD_CR80/4, 0x64
	,ZD_CR81/4, 0x64
	,ZD_CR82/4, 0x00
	,ZD_CR83/4, 0x24
	,ZD_CR84/4, 0x04
	,ZD_CR85/4, 0x00
	,ZD_CR86/4, 0x0c
	,ZD_CR87/4, 0x12
	,ZD_CR88/4, 0x0c
	,ZD_CR89/4, 0x00
	,ZD_CR90/4, 0x58
	,ZD_CR91/4, 0x04
	,ZD_CR92/4, 0x00
	,ZD_CR93/4, 0x00
	,ZD_CR94/4, 0x01
	,ZD_CR95/4, 0x20 // ZD1211B
	,ZD_CR96/4, 0x50
	,ZD_CR97/4, 0x37
	,ZD_CR98/4, 0x35
	,ZD_CR99/4, 0x00
	,ZD_CR100/4, 0x01
	,ZD_CR101/4, 0x13
	,ZD_CR102/4, 0x27
	,ZD_CR103/4, 0x27
	,ZD_CR104/4, 0x18
	,ZD_CR105/4, 0x12
	,ZD_CR106/4, 0x04
	,ZD_CR107/4, 0x00
	,ZD_CR108/4, 0x0a
	,ZD_CR109/4, 0x27
	,ZD_CR110/4, 0x27
	,ZD_CR111/4, 0x27
	,ZD_CR112/4, 0x27
	,ZD_CR113/4, 0x27
	,ZD_CR114/4, 0x27
	,ZD_CR115/4, 0x26
	,ZD_CR116/4, 0x24
	,ZD_CR117/4, 0xfc
	,ZD_CR118/4, 0xfa
	,ZD_CR119/4, 0x1e
	,ZD_CR125/4, 0x90
	,ZD_CR126/4, 0x00
	,ZD_CR127/4, 0x00
	,ZD_CR128/4, 0x14
	,ZD_CR129/4, 0x12
	,ZD_CR130/4, 0x10
	,ZD_CR131/4, 0x0c
	,ZD_CR136/4, 0xdf
	,ZD_CR137/4, 0xa0
	,ZD_CR138/4, 0xa8
	,ZD_CR139/4, 0xb4
	,ZD_CR140/4, 0x98
	,ZD_CR141/4, 0x82
	,ZD_CR142/4, 0x53
	,ZD_CR143/4, 0x1c
	,ZD_CR144/4, 0x6c
	,ZD_CR147/4, 0x07
	,ZD_CR148/4, 0x40
	,ZD_CR149/4, 0x40 // Org:0x50 //ComTrend:RalLink AP
	,ZD_CR150/4, 0x14//Org:0x0E //ComTrend:RalLink AP
	,ZD_CR151/4, 0x18
	,ZD_CR159/4, 0x70
	,ZD_CR160/4, 0xfe
	,ZD_CR161/4, 0xee
	,ZD_CR162/4, 0xaa
	,ZD_CR163/4, 0xfa
	,ZD_CR164/4, 0xfa
	,ZD_CR165/4, 0xea
	,ZD_CR166/4, 0xbe
	,ZD_CR167/4, 0xbe
	,ZD_CR168/4, 0x6a
	,ZD_CR169/4, 0xba
	,ZD_CR170/4, 0xba
	,ZD_CR171/4, 0xba
	,ZD_CR204/4, 0x7d	// Note: CR204 must lead the CR203
	,ZD_CR203/4, 0x30
};
	LockPhyReg(pObj);
    for(i=0;i<(sizeof(RegVal)/sizeof(RegVal[0]))/2;i++)
        pObj->SetReg(pObj, RegVal[i*2]*4, RegVal[i*2+1]);

	// Release Phy-Config permission
    //if (pObj->ChipVer == ZD_1211B)
    {
        if (pObj->HWFeature & BIT_13) //6321 Bin 4 Tx IQ balance for ZD1212 only
        {
            phyOverwrite = pObj->GetReg(reg, E2P_PHY_REG);   
            pObj->SetReg(reg, ZD_CR157, ((phyOverwrite >> 8) & 0xff));  
            phyOverwrite = pObj->GetReg(reg, ZD_CR157); 
            printk(KERN_DEBUG "OverWrite CR157 = 0x%X\n", phyOverwrite & 0xff);
        }
    }
    if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
    {
        phyOverwrite = pObj->GetReg(reg, E2P_PHY_REG);
        pObj->SetReg(reg, ZD_CR47, (phyOverwrite & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
        phyOverwrite = pObj->GetReg(reg, ZD_CR47); 
        printk(KERN_DEBUG "OverWrite CR47 = 0x%X\n", phyOverwrite & 0xFF);
    }

    UnLockPhyReg(pObj);


	return;
#if 0
    void *reg = pObj->reg;
	u32	tmpvalue;
    U32 phyOverwrite;

	// Get Phy-Config permission
	LockPhyReg(pObj);

	pObj->SetReg(reg,ZD_CR0, 0x14);
	pObj->SetReg(reg,ZD_CR1, 0x06);
	pObj->SetReg(reg,ZD_CR2, 0x26);
	pObj->SetReg(reg,ZD_CR3, 0x38);
	pObj->SetReg(reg,ZD_CR4, 0x80);
	pObj->SetReg(reg,ZD_CR9, 0xe0);
	pObj->SetReg(reg,ZD_CR10, 0x81);
	//``JWEI 2003/12/26
#if fTX_PWR_CTRL && fTX_GAIN_OFDM
	pObj->SetReg(reg, ZD_CR11, BIT_6);
#else
	pObj->SetReg(reg,ZD_CR11, 0x00);
#endif
	pObj->SetReg(reg,ZD_CR12, 0xf0);
	pObj->SetReg(reg,ZD_CR13, 0x8c);
	pObj->SetReg(reg,ZD_CR14, 0x80);
	pObj->SetReg(reg,ZD_CR15, 0x3d);
	pObj->SetReg(reg,ZD_CR16, 0x20);
	pObj->SetReg(reg,ZD_CR17, 0x1e);
	pObj->SetReg(reg,ZD_CR18, 0x0a);
	pObj->SetReg(reg,ZD_CR19, 0x48);
	pObj->SetReg(reg,ZD_CR20, 0x10);//Org:0x0E,ComTrend:RalLink AP
	pObj->SetReg(reg,ZD_CR21, 0x0e);
	pObj->SetReg(reg,ZD_CR22, 0x23);
	pObj->SetReg(reg,ZD_CR23, 0x90);
	pObj->SetReg(reg,ZD_CR24, 0x14);
	pObj->SetReg(reg,ZD_CR25, 0x40);
	pObj->SetReg(reg,ZD_CR26, 0x10);
	pObj->SetReg(reg,ZD_CR27, 0x10);
	pObj->SetReg(reg,ZD_CR28, 0x7f);
	pObj->SetReg(reg,ZD_CR29, 0x80);
#ifndef ASIC
	// For FWT
	pObj->SetReg(reg,ZD_CR30, 0x4b);
#else
	// For Jointly decoder
	pObj->SetReg(reg,ZD_CR30, 0x49);
#endif
	pObj->SetReg(reg,ZD_CR31, 0x60);
	pObj->SetReg(reg,ZD_CR32, 0x43);
	pObj->SetReg(reg,ZD_CR33, 0x08);
	pObj->SetReg(reg,ZD_CR34, 0x06);
	pObj->SetReg(reg,ZD_CR35, 0x0a);
	pObj->SetReg(reg,ZD_CR36, 0x00);
	pObj->SetReg(reg,ZD_CR37, 0x00);
	pObj->SetReg(reg,ZD_CR38, 0x38);
	pObj->SetReg(reg,ZD_CR39, 0x0c);
	pObj->SetReg(reg,ZD_CR40, 0x84);
	pObj->SetReg(reg,ZD_CR41, 0x2a);
	pObj->SetReg(reg,ZD_CR42, 0x80);
	pObj->SetReg(reg,ZD_CR43, 0x10);
	pObj->SetReg(reg,ZD_CR44, 0x33);
	pObj->SetReg(reg,ZD_CR46, 0xff);
	pObj->SetReg(reg,ZD_CR47, 0x1E);
	pObj->SetReg(reg,ZD_CR48, 0x26);
	pObj->SetReg(reg,ZD_CR49, 0x5b);
	pObj->SetReg(reg,ZD_CR64, 0xd0);
	pObj->SetReg(reg,ZD_CR65, 0x04);
	pObj->SetReg(reg,ZD_CR66, 0x58);
	pObj->SetReg(reg,ZD_CR67, 0xc9);
	pObj->SetReg(reg,ZD_CR68, 0x88);
	pObj->SetReg(reg,ZD_CR69, 0x41);
	pObj->SetReg(reg,ZD_CR70, 0x23);
	pObj->SetReg(reg,ZD_CR71, 0x10);
	pObj->SetReg(reg,ZD_CR72, 0xff);
	pObj->SetReg(reg,ZD_CR73, 0x32);
	pObj->SetReg(reg,ZD_CR74, 0x30);
	pObj->SetReg(reg,ZD_CR75, 0x65);
	pObj->SetReg(reg,ZD_CR76, 0x41);
	pObj->SetReg(reg,ZD_CR77, 0x1b);
	pObj->SetReg(reg,ZD_CR78, 0x30);
	pObj->SetReg(reg,ZD_CR79, 0xf0);
	pObj->SetReg(reg,ZD_CR80, 0x64);
	pObj->SetReg(reg,ZD_CR81, 0x64);
	pObj->SetReg(reg,ZD_CR82, 0x00);
	pObj->SetReg(reg,ZD_CR83, 0x24);
	pObj->SetReg(reg,ZD_CR84, 0x04);
	pObj->SetReg(reg,ZD_CR85, 0x00);
	pObj->SetReg(reg,ZD_CR86, 0x0c);
	pObj->SetReg(reg,ZD_CR87, 0x12);
	pObj->SetReg(reg,ZD_CR88, 0x0c);
	pObj->SetReg(reg,ZD_CR89, 0x00);
	pObj->SetReg(reg,ZD_CR90, 0x58);
	pObj->SetReg(reg,ZD_CR91, 0x04);
	pObj->SetReg(reg,ZD_CR92, 0x00);
	pObj->SetReg(reg,ZD_CR93, 0x00);
	pObj->SetReg(reg,ZD_CR94, 0x01);
	pObj->SetReg(reg,ZD_CR95, 0x20); // ZD1211B
	pObj->SetReg(reg,ZD_CR96, 0x50);
	pObj->SetReg(reg,ZD_CR97, 0x37);
	pObj->SetReg(reg,ZD_CR98, 0x35);
	pObj->SetReg(reg,ZD_CR99, 0x00);
	pObj->SetReg(reg,ZD_CR100, 0x01);
	pObj->SetReg(reg,ZD_CR101, 0x13);
	pObj->SetReg(reg,ZD_CR102, 0x27);
	pObj->SetReg(reg,ZD_CR103, 0x27);
	pObj->SetReg(reg,ZD_CR104, 0x18);
	pObj->SetReg(reg,ZD_CR105, 0x12);
	pObj->SetReg(reg,ZD_CR106, 0x04);
	pObj->SetReg(reg,ZD_CR107, 0x00);
	pObj->SetReg(reg,ZD_CR108, 0x0a);
	pObj->SetReg(reg,ZD_CR109, 0x27);
	pObj->SetReg(reg,ZD_CR110, 0x27);
	pObj->SetReg(reg,ZD_CR111, 0x27);
	pObj->SetReg(reg,ZD_CR112, 0x27);
	pObj->SetReg(reg,ZD_CR113, 0x27);
	pObj->SetReg(reg,ZD_CR114, 0x27);
	pObj->SetReg(reg,ZD_CR115, 0x26);
	pObj->SetReg(reg,ZD_CR116, 0x24);
	pObj->SetReg(reg,ZD_CR117, 0xfc);
	pObj->SetReg(reg,ZD_CR118, 0xfa);
	pObj->SetReg(reg,ZD_CR119, 0x1e);
	pObj->SetReg(reg,ZD_CR125, 0x90);
	pObj->SetReg(reg,ZD_CR126, 0x00);
	pObj->SetReg(reg,ZD_CR127, 0x00);
	pObj->SetReg(reg,ZD_CR128, 0x14);
	pObj->SetReg(reg,ZD_CR129, 0x12);
	pObj->SetReg(reg,ZD_CR130, 0x10);
	pObj->SetReg(reg,ZD_CR131, 0x0c);
	pObj->SetReg(reg,ZD_CR136, 0xdf);
	pObj->SetReg(reg,ZD_CR137, 0xa0);
	pObj->SetReg(reg,ZD_CR138, 0xa8);
	pObj->SetReg(reg,ZD_CR139, 0xb4);
	pObj->SetReg(reg,ZD_CR140, 0x98);
	pObj->SetReg(reg,ZD_CR141, 0x82);
	pObj->SetReg(reg,ZD_CR142, 0x53);
	pObj->SetReg(reg,ZD_CR143, 0x1c);
	pObj->SetReg(reg,ZD_CR144, 0x6c);
	pObj->SetReg(reg,ZD_CR147, 0x07);
	pObj->SetReg(reg,ZD_CR148, 0x40);
	pObj->SetReg(reg,ZD_CR149, 0x40); // Org:0x50 //ComTrend:RalLink AP
	pObj->SetReg(reg,ZD_CR150, 0x14);//Org:0x0E //ComTrend:RalLink AP
	pObj->SetReg(reg,ZD_CR151, 0x18);
	pObj->SetReg(reg,ZD_CR159, 0x70);
	pObj->SetReg(reg,ZD_CR160, 0xfe);
	pObj->SetReg(reg,ZD_CR161, 0xee);
	pObj->SetReg(reg,ZD_CR162, 0xaa);
	pObj->SetReg(reg,ZD_CR163, 0xfa);
	pObj->SetReg(reg,ZD_CR164, 0xfa);
	pObj->SetReg(reg,ZD_CR165, 0xea);
	pObj->SetReg(reg,ZD_CR166, 0xbe);
	pObj->SetReg(reg,ZD_CR167, 0xbe);
	pObj->SetReg(reg,ZD_CR168, 0x6a);
	pObj->SetReg(reg,ZD_CR169, 0xba);
	pObj->SetReg(reg,ZD_CR170, 0xba);
	pObj->SetReg(reg,ZD_CR171, 0xba);
	// Note: CR204 must lead the CR203
	pObj->SetReg(reg,ZD_CR204, 0x7d);
	pObj->SetReg(reg,ZD_CR203, 0x30);

	// Release Phy-Config permission
    //if (pObj->ChipVer == ZD_1211B)
    {
        if (pObj->HWFeature & BIT_13) //6321 Bin 4 Tx IQ balance for ZD1212 only
        {
            phyOverwrite = pObj->GetReg(reg, E2P_PHY_REG);   
            pObj->SetReg(reg, ZD_CR157, ((phyOverwrite >> 8) & 0xff));  
            phyOverwrite = pObj->GetReg(reg, ZD_CR157); 
            printk(KERN_DEBUG "OverWrite CR157 = 0x%X\n", phyOverwrite & 0xff);
        }
    }
    if (pObj->HWFeature & BIT_8) //CR47 CCK gain patch
    {
        phyOverwrite = pObj->GetReg(reg, E2P_PHY_REG);
        pObj->SetReg(reg, ZD_CR47, (phyOverwrite & 0xff)); //This feature is OK to be overwritten with a lower value by other feature
        phyOverwrite = pObj->GetReg(reg, ZD_CR47); 
        printk(KERN_DEBUG "OverWrite CR47 = 0x%X\n", phyOverwrite & 0xFF);
    }

    UnLockPhyReg(pObj);


	return;
#endif
}

#endif

void HW_InitHMAC(zd_80211Obj_t *pObj)
{
	void *reg = pObj->reg;

	// Set GPI_EN be zero. ie. Disable GPI (Requested by Ahu)
	//pObj->SetReg(reg, ZD_GPI_EN, 0x00);
	
	// Use Ack_Timeout_Ext to tolerance some peers that response slowly.
	// The influence is that the retry frame will be less competitive. It's acceptable.
	pObj->SetReg(reg, ZD_Ack_Timeout_Ext, 0x20); //only bit0-bit5 are valid

	pObj->SetReg(reg, ZD_ADDA_MBIAS_WarmTime, 0x30000808);
	
	/* Set RetryMax 8 */
#ifdef ZD1211
	pObj->SetReg(reg, ZD_RetryMAX, 0x2);
#elif defined(ZD1211B) 
	pObj->SetReg(reg, ZD_RetryMAX, 0x02020202);

	pObj->SetReg(reg,0xB0C,0x007f003f);
	pObj->SetReg(reg,0xB08,0x007f003f);
	pObj->SetReg(reg,0xB04,0x003f001f);
	pObj->SetReg(reg,0xB00,0x001f000f);
	//set AIFS AC0 - AC3	
	pObj->SetReg(reg,0xB10,0x00280028);
	pObj->SetReg(reg,0xB14,0x008C003C);
	//set TXOP AC0 - AC3	
	pObj->SetReg(reg,0xB20,0x01800824);
	//pObj->SetReg(reg,0xB20,0x00800a28);

#endif

	/* Turn off sniffer mode */	
	pObj->SetReg(reg, ZD_SnifferOn, 0);

	/* Set Rx filter*/
	// filter Beacon and unfilter PS-Poll
	pObj->SetReg(reg, ZD_Rx_Filter, AP_RX_FILTER);

	/* Set Hashing table */
	pObj->SetReg(reg, ZD_GroupHash_P1, 0x00);
	pObj->SetReg(reg, ZD_GroupHash_P2, 0x80000000);
	
	pObj->SetReg(reg, ZD_CtlReg1, 0xa4);
	pObj->SetReg(reg, ZD_ADDA_PwrDwn_Ctrl, 0x7f); 
	
	/* Initialize BCNATIM needed registers */	
	pObj->SetReg(reg, ZD_BCNPLCPCfg, 0x00f00401);
	pObj->SetReg(reg, ZD_PHYDelay, 0x00);
	
#if defined(OFDM)
	#ifdef HOST_IF_USB
        pObj->SetReg(reg, ZD_Ack_Timeout_Ext, 0x80);
		pObj->SetReg(reg, ZD_ADDA_PwrDwn_Ctrl, 0x0); 
	#endif
		
	//pObj->SetReg(reg, ZD_AckTime80211, 0x102);
	pObj->SetReg(reg, ZD_AckTime80211, 0x100);
	pObj->SetReg(reg, ZD_IFS_Value, 0xa47c032); //0x547c032
	
	// accept beacon for enable protection mode

	//pObj->SetReg(reg, ZD_Rx_Filter, ((BIT_10 << 16) | (0xffff))); 
	//pObj->SetReg(reg, ZD_Rx_Filter, ((BIT_10 << 16) | (0xffff & ~BIT_8))); //for pure G debug
	
	// Set RX_PE_DELAY 0x10 to enlarge the time for decharging tx power.
	pObj->SetReg(reg, ZD_RX_PE_DELAY, 0x70);
	
	//pObj->SetReg(reg, ZD_SnifferOn, 0x3000000); //enable HW Rx Retry filter, and HW MIC
	//pObj->SetReg(reg, ZD_Rx_OFFSET, 0x03); //to fit MIC engine's 4 byte alignment
	
	// Keep 44MHz oscillator always on.
	pObj->SetReg(reg, ZD_PS_Ctrl, 0x10000000);
#endif


#if defined(AMAC)
	#if defined(ECCK_60_5)
		pObj->SetReg(reg, ZD_RTS_CTS_Rate, 0x00);
	#elif (defined(GCCK) && defined(OFDM))	
		//pObj->SetReg(reg, ZD_RTS_CTS_Rate, 0x30000);
		pObj->SetReg(reg, ZD_RTS_CTS_Rate, 0x2030203);
	#endif	
	
	// Set Rx Threshold
#ifdef ZD1211B
	pObj->SetReg(reg, ZD_RX_THRESHOLD, 0x000c0eff);
#else
	pObj->SetReg(reg, ZD_RX_THRESHOLD, 0x000c0640);
#endif
	
	// Set Tx-Pwr-Control registers
	//pObj->SetReg(reg, ZD_TX_PWR_CTRL_1, 0x7f7f7f7f);
	//pObj->SetReg(reg, ZD_TX_PWR_CTRL_2, 0x7c7f7f7f);
	//pObj->SetReg(reg, ZD_TX_PWR_CTRL_3, 0x6c6c747c);
	//pObj->SetReg(reg, ZD_TX_PWR_CTRL_4, 0x00006064);
	
#ifdef HOST_IF_USB
	pObj->SetReg(reg, ZD_AfterPNP, 0x1);
	pObj->SetReg(reg, ZD_Wep_Protect, 0x114);
#else
	pObj->SetReg(reg, ZD_AfterPNP, 0x64009);
	pObj->SetReg(reg, ZD_Wep_Protect, 0x118); //4315 for TKIP key mixing
#endif	
#endif
}
// This function is obsolete since version of 2.18.0.1
void HW_OverWritePhyRegFromE2P(zd_80211Obj_t *pObj)
{
	U32 tmpvalue;
	void *reg = pObj->reg;

	//if (!pObj->bOverWritePhyRegFromE2P) 
		return;
#if 0
	LockPhyReg(pObj);
	tmpvalue = pObj->GetReg(reg, E2P_PHY_REG);
	pObj->SetReg(reg, ZD_CR47, (tmpvalue & 0xFF));
    printk("HW_OverWritePhyRegFromE2P: Over write CR47 with 0x%X\n", tmpvalue & 0xff);
	UnLockPhyReg(pObj);
	return;
#endif
}
#if 0
void HW_WritePhyReg(zd_80211Obj_t *pObj, U8 PhyIdx, U8 PhyValue)
{
	U32	IoAddress;
	void *reg = pObj->reg;

	switch(PhyIdx){
		case 4:
			IoAddress = 0x20;
			break;
			
		case 5:
			IoAddress = 0x10;
			break;
			
		case 6:
			IoAddress = 0x14;
			break;

		case 7:
			IoAddress = 0x18;
			break;			

		case 8:
			IoAddress = 0x1C;
			break;

		default:
			IoAddress = (((U32)PhyIdx) << 2);

			break;
	}

	LockPhyReg(pObj);
	pObj->SetReg(reg, IoAddress, PhyValue);
	UnLockPhyReg(pObj);
}
#endif


void HW_UpdateIntegrationValue(zd_80211Obj_t *pObj, U32 ChannelNo, const U8 MAC_Mode)
{
	void *reg = pObj->reg;
	struct zd1205_private *macp = (struct zd1205_private *) netdev_priv(g_dev);
	U32	tmpvalue;
	u8 Useless_set, intV;

    if(macp->RF_Mode == UW2453_RF || macp->RF_Mode == AR2124_RF)
        return;
#ifdef HOST_IF_USB

	//tmpvalue = pObj->GetReg(reg, ZD_E2P_PWR_INT_VALUE1+((ChannelNo-1) & 0xc));
	//tmpvalue = (U8) (tmpvalue >> (((ChannelNo - 1) % 4) * 8));
	if(PURE_A_MODE != MAC_Mode)
		tmpvalue = pObj->IntValue[ChannelNo - 1];
#if ZDCONF_80211A_SUPPORT == 1
	else if(PURE_A_MODE == MAC_Mode) {
		a_OSC_get_cal_int(ChannelNo, RATE_54M,&intV,&Useless_set); 	
		tmpvalue = intV;
	}
#endif
	else
		VerAssert();
	HW_Write_TxGain1(pObj, (U8) tmpvalue, cTX_CCK);
#endif
#ifdef ZD1211B
	LockPhyReg(pObj);
	if(PURE_A_MODE != MAC_Mode) {
		pObj->SetReg(reg,ZD_CR65,macp->SetPointOFDM[2][ChannelNo-1]);
		pObj->SetReg(reg,ZD_CR66,macp->SetPointOFDM[1][ChannelNo-1]);
		pObj->SetReg(reg,ZD_CR67,macp->SetPointOFDM[0][ChannelNo-1]);
		pObj->SetReg(reg,ZD_CR68,macp->EepSetPoint[ChannelNo-1]);
	}
#if ZDCONF_80211A_SUPPORT == 1
	else {
		u8 set36,set48,set54, intValue;
		a_OSC_get_cal_int( ChannelNo, RATE_54M, &intValue, &set54);
		a_OSC_get_cal_int( ChannelNo, RATE_48M, &intValue, &set48);
		a_OSC_get_cal_int( ChannelNo, RATE_36M, &intValue, &set36);
        pObj->SetReg(reg,ZD_CR65,set54);
        pObj->SetReg(reg,ZD_CR66,set48);
        pObj->SetReg(reg,ZD_CR67,set36);
        pObj->SetReg(reg,ZD_CR68,macp->EepSetPoint[ChannelNo-1]);
	}
#endif

	pObj->SetReg(reg,ZD_CR69,0x28);
	pObj->SetReg(reg,ZD_CR69,0x2a);

	UnLockPhyReg(pObj);
#endif
}

void HW_Write_TxGain(zd_80211Obj_t *pObj, U32 txgain)
{
	U32	tmpvalue;
	void *reg = pObj->reg;
	U8	i;

	switch(pObj->rfMode){
/*
		case GCT_RF:
			txgain &= 0x3f;

			//FPRINT_V("Set tx gain", txgain);
			tmpvalue = 0;
			// Perform Bit-Reverse
			for (i=0; i<6; i++){
				if (txgain & BIT_0){
					tmpvalue |= (0x1 << (15-i));
				}
				txgain = (txgain >> 1);
			}
			tmpvalue |= 0x0c0000;
			HW_Set_IF_Synthesizer(pObj, tmpvalue);
			//FPRINT_V("HW_Set_IF_Synthesizer", tmpvalue);
			HW_Set_IF_Synthesizer(pObj, 0x150800);
			HW_Set_IF_Synthesizer(pObj, 0x150000);
			break;
*/
			
#if 0
		case AL2210_RF:	
		case AL2210MPVB_RF:
			if (txgain > AL2210_MAX_TX_PWR_SET){
				txgain = AL2210_MAX_TX_PWR_SET;
			}
			else if (txgain < AL2210_MIN_TX_PWR_SET){
				txgain = AL2210_MIN_TX_PWR_SET;
			}
			
			LockPhyReg(pObj);
			pObj->SetReg(reg, ZD_CR31, (U8)txgain);
			UnLockPhyReg(pObj);
			break;	
#endif
			
		default:
			break;
	}
}


void HW_Write_TxGain0(zd_80211Obj_t *pObj, U8 *pTxGain, U8 TxPwrType)
{
	void *reg = pObj->reg;

	switch (pObj->rfMode){
/*
	case MAXIM_NEW_RF:                 
		*pTxGain &= MAXIM2_MAX_TX_PWR_SET;
		LockPhyReg(pObj);

		if (TxPwrType != cTX_OFDM){
			pObj->SetReg(reg, ZD_CR31, *pTxGain);
		}
		else{
#if !fTX_GAIN_OFDM
			pObj->SetReg(reg, ZD_CR31, *pTxGain);
#else
			pObj->SetReg(reg, ZD_CR51, *pTxGain);
			pObj->SetReg(reg, ZD_CR52, *pTxGain);
			pObj->SetReg(reg, ZD_CR53, *pTxGain);
#endif
		}
		UnLockPhyReg(pObj);
		break;
*/
            
	case RFMD_RF:                 
	case AL2230_RF:
	case AL7230B_RF:
    case AL2230S_RF:
		LockPhyReg(pObj);
		if (TxPwrType != cTX_OFDM){
			pObj->SetReg(reg, ZD_CR31, *pTxGain);
		}
		else {
#if !fTX_GAIN_OFDM
			pObj->SetReg(reg, ZD_CR31, *pTxGain);
#else
			pObj->SetReg(reg, ZD_CR51, *pTxGain);
			pObj->SetReg(reg, ZD_CR52, *pTxGain);
			pObj->SetReg(reg, ZD_CR53, *pTxGain);
#endif
		}
		UnLockPhyReg(pObj);
		break;
	default:
		break;
	}
}

void HW_Write_TxGain1(zd_80211Obj_t *pObj, U8 txgain, U8 TxPwrType)
{
	U8   *pTxGain;

	HW_Write_TxGain0(pObj, &txgain, TxPwrType);

#if fTX_GAIN_OFDM
	if (TxPwrType != cTX_OFDM)
		pTxGain = &(pObj->TxGainSetting);
	else
		pTxGain = &(pObj->TxGainSetting2);
#else
	pTxGain = &(pObj->TxGainSetting);
#endif

	*pTxGain = txgain;
}

void HW_Write_TxGain2(zd_80211Obj_t *pObj, U8 TxPwrType)
{
	U8   *pTxGain;


    if (TxPwrType != cTX_OFDM){
        pTxGain = &(pObj->TxGainSetting);
    }
    else
    {
    #if fTX_GAIN_OFDM
        pTxGain = &(pObj->TxGainSetting2);
    #else
        pTxGain = &(pObj->TxGainSetting);
    #endif
    }
    
    HW_Write_TxGain0(pObj, pTxGain, TxPwrType);
}

void HW_Set_FilterBand(zd_80211Obj_t *pObj, U32	region_code)
{
	U32	tmpLong;
	void *reg = pObj->reg;

	switch(region_code){
		case 0x40:	// Japan
			LockPhyReg(pObj);
			//if (pObj->rfMode == MAXIM_NEW_RF) 
			{
				tmpLong = pObj->GetReg(reg, ZD_CR5);
				tmpLong |= BIT_6;	//japan
				pObj->SetReg(reg, ZD_CR5, tmpLong);
			}	
		
			UnLockPhyReg(pObj);
			break;
			
		default:
			LockPhyReg(pObj);
			tmpLong = pObj->GetReg(reg, ZD_CR5);
			tmpLong &= ~BIT_6;//USA

			pObj->SetReg(reg, ZD_CR5, tmpLong);
			UnLockPhyReg(pObj);
			break;
	}
}


void HW_UpdateBcnInterval(zd_80211Obj_t *pObj, U16 BcnInterval)
{
	void *reg = pObj->reg;
	U32	tmpvalue;
	U32	ul_PreTBTT;
	U32	ul_ATIMWnd;


	//++ 
	// Make sure that BcnInterval > Pre_TBTT > ATIMWnd >= 0
	if (BcnInterval < 5){
		BcnInterval = 5;
	}

	ul_PreTBTT = pObj->GetReg(reg, ZD_Pre_TBTT);
	if (ul_PreTBTT < 4){
		ul_PreTBTT = 4;
	}
	
	if (ul_PreTBTT >= BcnInterval){
		ul_PreTBTT = BcnInterval-1;

	}
	pObj->SetReg(reg, ZD_Pre_TBTT, ul_PreTBTT);

	ul_ATIMWnd = pObj->GetReg(reg, ZD_ATIMWndPeriod);
	if (ul_ATIMWnd >= ul_PreTBTT){
		ul_ATIMWnd = ul_PreTBTT-1;
	}
	pObj->SetReg(reg, ZD_ATIMWndPeriod, ul_ATIMWnd);

	tmpvalue = pObj->GetReg(reg, ZD_BCNInterval);
	tmpvalue &= ~0xffff;
	tmpvalue |= BcnInterval;
	pObj->SetReg(reg, ZD_BCNInterval, tmpvalue);
	
	pObj->BeaconInterval = BcnInterval;
}



#if ZDCONF_ADHOC_SUPPORT == 1
void HW_UpdateATIMWindow(zd_80211Obj_t *pObj, U16 AtimWnd)
{
	void *reg = pObj->reg;
	U32	ul_PreTBTT;

	//++ 
	// Make sure that Pre_TBTT > ATIMWnd >= 0

	ul_PreTBTT = pObj->GetReg(reg, ZD_Pre_TBTT);
	if (AtimWnd >= ul_PreTBTT){
		AtimWnd = (U16)(ul_PreTBTT-1);
	}
	//--
	
	pObj->SetReg(reg, ZD_ATIMWndPeriod, AtimWnd);
}
#endif


void HW_UpdatePreTBTT(zd_80211Obj_t *pObj, U32 pretbtt)
{
	void *reg = pObj->reg;
	U32	ul_BcnItvl;
	U32	ul_AtimWnd;

	//++ 
	// Make sure that BcnInterval > Pre_TBTT > ATIMWnd 
	ul_BcnItvl = pObj->GetReg(reg, ZD_BCNInterval);
	ul_BcnItvl &= 0xff;
	if (pretbtt >= ul_BcnItvl){
		pretbtt = ul_BcnItvl-1;
	}
	
	ul_AtimWnd = pObj->GetReg(reg, ZD_ATIMWndPeriod);
	if (pretbtt <= ul_AtimWnd){
		pretbtt = ul_AtimWnd+1;
	}
	//--

	pObj->SetReg(reg, ZD_Pre_TBTT, pretbtt);
}

// for AMAC CAM operation
void HW_CAM_Avail(zd_80211Obj_t *pObj)
{
	void *reg = pObj->reg;
	U32 tmpValue;
    U16 loopCheck = 0;
	
	tmpValue = pObj->GetReg(reg, ZD_CAM_MODE);
	while(tmpValue & HOST_PEND){
        // To WAIT HW Ready when set encryption key
        // Wait too long is abnormal.
        if(loopCheck++ > 100)
        {
            printk("infinite loop occurs in %s\n", __FUNCTION__);
            loopCheck = 0;
            break;
        }

		pObj->DelayUs(10);
		tmpValue = pObj->GetReg(reg, ZD_CAM_MODE);
	}
}

void HW_CAM_Write(zd_80211Obj_t *pObj, U32 address, U32 data)
{
    void *reg = pObj->reg;
    U32 tmpValue;
    if(mBssType == AP_BSS)
    {
        tmpValue = pObj->GetReg(reg, ZD_CAM_MODE);
        tmpValue |= BIT_8;
        pObj->SetReg(reg, ZD_CAM_MODE,tmpValue);
    }
        
    HW_CAM_Avail(pObj);
    pObj->SetReg(reg, ZD_CAM_DATA, data);
    HW_CAM_Avail(pObj);
    pObj->SetReg(reg, ZD_CAM_ADDRESS, (address | CAM_WRITE));

    if(mBssType == AP_BSS)
    {
        tmpValue = pObj->GetReg(reg, ZD_CAM_MODE);
        tmpValue &= ~BIT_8;
        pObj->SetReg(reg, ZD_CAM_MODE,tmpValue);
    }

}

U32 HW_CAM_Read(zd_80211Obj_t *pObj, U32 address)
{
    void *reg = pObj->reg;
    U32 result,tmpValue;

    
    if(mBssType == AP_BSS)
    {
        tmpValue = pObj->GetReg(reg, ZD_CAM_MODE);
        tmpValue |= BIT_8;
        pObj->SetReg(reg, ZD_CAM_MODE,tmpValue);
    }

    HW_CAM_Avail(pObj);
    pObj->SetReg(reg, ZD_CAM_ADDRESS, address);
    HW_CAM_Avail(pObj);
    result = pObj->GetReg(reg, ZD_CAM_DATA);

//Need to do this twice. This is a hw bug.
    HW_CAM_Avail(pObj);
    pObj->SetReg(reg, ZD_CAM_ADDRESS, address);
    HW_CAM_Avail(pObj);
    result = pObj->GetReg(reg, ZD_CAM_DATA);

    if(mBssType == AP_BSS)
    {
        tmpValue = pObj->GetReg(reg, ZD_CAM_MODE);
        tmpValue &= ~BIT_8;
        pObj->SetReg(reg, ZD_CAM_MODE,tmpValue);
    }
    return result;

}	

void HW_CAM_SetMAC(zd_80211Obj_t *pObj, U16 aid, U8 *pMAC)
{
	U32 userWordAddr;
	U32 userByteOffset;
	U32 tmpValue;
	int i;
    
	userWordAddr = (aid/4)*6;
	userByteOffset = aid % 4;
    if(mBssType == INFRASTRUCTURE_BSS && mWPAIe[1] != 0 && (aid == 0 || aid == 8))
    {// Assume aid 0 is used for Pairwise key, aid 8 is used for Group key.
     // aid 0 use the LSB of location 0 to location 5.
     // aid 8 use the LSB of location 12 to location 17.i
     // According to the above assumptions, userByteOffset = 0.
     //   We also clear the setting value of user 1 to 3 when set aid 0.
     //   We also clear the setting value of user 9 to 11 when set aid 8.
        WPADEBUG("...for Infra-STA, quick write MAC to CAM for aid %d\n", aid);
        for (i=0; i<MAC_LENGTH; i++)
        {
            HW_CAM_Write(pObj, (userWordAddr+i), pMAC[i]);
        }
        return;
    }
        
	
	for (i=0; i<MAC_LENGTH; i++) {
		tmpValue = HW_CAM_Read(pObj, (userWordAddr+i));
		tmpValue &= (~(0xff << (userByteOffset*8)));
		tmpValue |= (pMAC[i]<<(userByteOffset*8));
		HW_CAM_Write(pObj, (userWordAddr+i), tmpValue);
	}
}		


void HW_CAM_GetMAC(zd_80211Obj_t *pObj, U16 aid, U8 *pMac)
{
	U32 userWordAddr;
	U32 userByteOffset;
	U32 tmpValue;
	U8 mac[6];
	int i;	
	
	userWordAddr = (aid/4)*6;
	userByteOffset = aid % 4;
	
	for (i=0; i<MAC_LENGTH; i++) {
		tmpValue = HW_CAM_Read(pObj, (userWordAddr+i));
		pMac[i] = (U8)(tmpValue >> (userByteOffset*8)) & 0xFF;
	}	
			
	if (memcmp(mac, pMac, 6) != 0){
		FPRINT("*****Where is my MAC ????");		
	}	
	else
		FPRINT("*****Verify MAC OK!!!");	
}	


void HW_CAM_SetEncryType(zd_80211Obj_t *pObj, U16 aid, U8 encryType)
{
	U32 encryWordAddr;
	U32 encryByteOffset;
	U32 tmpValue;	

	U8 targetByte;
	
	encryWordAddr = ENCRY_TYPE_START_ADDR + (aid/8);
	encryByteOffset = (aid/2) % 4; 
	
	tmpValue = HW_CAM_Read(pObj, encryWordAddr);
	targetByte = (U8)(tmpValue >> (encryByteOffset*8)); 
	tmpValue &= ~(0xff << (encryByteOffset*8)); //clear target byte
	if (aid % 2) 
		targetByte = (encryType<<4) | (targetByte & 0xf); //set hignt part
	else //low nibble
		targetByte = encryType | (targetByte & 0xf0); //set low part
			
	tmpValue |= targetByte << (encryByteOffset*8);


	HW_CAM_Write(pObj, encryWordAddr, tmpValue);
}	


U8 HW_CAM_GetEncryType(zd_80211Obj_t *pObj, U16 aid)
{
	U32 encryWordAddr;
	U32 encryByteOffset;

	U32 tmpValue;
	U8 keyLength = 0;
	U8 targetByte;
	
	encryWordAddr = ENCRY_TYPE_START_ADDR + (aid/8);
	encryByteOffset = (aid/2) % 4;
	
	tmpValue = HW_CAM_Read(pObj, encryWordAddr);
	targetByte = (U8)(tmpValue >> (encryByteOffset*8)); 
	if (aid % 2)
		targetByte >>= 4; //get hignt part
	else
		targetByte &= 0x0f; //get low part
	
	switch(targetByte){ 
		case NO_WEP: //0
			FPRINT("***No Encryption");
			break;
		
		case WEP64: //1
			FPRINT("***WEP 64");
			keyLength = 5;
			break;
		
		case TKIP: //2
			FPRINT("**TKIP");
			keyLength = 16;
			break;
		
		case AES: //4

			FPRINT("***CCM");
			keyLength = 16;
			break;	
			

		case WEP128: //5
			FPRINT("***WEP 128");
			keyLength = 13;
			break;	
			
		default:
			FPRINT("***Not Supported Encry");
			break;				
	}		
	
	//return keyLength;
    return targetByte;

}		


void HW_CAM_SetKey(zd_80211Obj_t *pObj, U16 aid, U8 keyLength, U8 *pKey)
{

    U32 keyWordAddr;
    U8 offset;
    U32 tmpValue;
    int i,j,k;

    keyWordAddr = KEY_START_ADDR + (aid*8);

    offset = 0;
    for(i=0;i<8;i++)        
    {
        tmpValue = HW_CAM_Read(pObj, (keyWordAddr+i));
        for(j=offset,k=0;k<4;j++,k++)
        {
            tmpValue &= ~(0xff << (k*8));
            if(offset < keyLength)
            {
                tmpValue |= pKey[j] << (k*8);
            }
            offset++;
        }
        HW_CAM_Write(pObj, (keyWordAddr+i), tmpValue);
    }
/*
	U32 keyWordAddr;
	U32 tmpValue;
	int i, j, k;
	
	keyWordAddr = KEY_START_ADDR + (aid*8);
	
        j = 0;	
        for (i=0; i < (keyLength+3)/4; i++)
        {
            //tmpValue = HW_CAM_Read(pObj, (keyWordAddr+i));
            tmpValue = 0;
            for (k=0; k<4; k++) 
            {  // j: the byte offset of pKey.
               //tmpValue &= ~(0xff << (k*8));
               if (j < keyLength)
               {
                   tmpValue |= pKey[j] << (k*8);
               }
               j++;
            }
            HW_CAM_Write(pObj, (keyWordAddr+i), tmpValue);
        }	
*/

}	


void HW_CAM_GetKey(zd_80211Obj_t *pObj, U16 aid, U8 keyLength, U8 *pKey)
{
	U32 keyWordAddr;
	U8 key[32];
	int i, j;
	U32 tmpValue;
	
	keyWordAddr = KEY_START_ADDR + (aid*8);
	j = 0;
	for (i=0; i<8; i++){
		tmpValue = HW_CAM_Read(pObj, (keyWordAddr+i));
		key[j] = (U8)(tmpValue);	
		j++;
		key[j] = (U8)(tmpValue >> 8);
		j++;
		key[j] = (U8)(tmpValue >> 16);
		j++;
		key[j] = (U8)(tmpValue >> 24);
		j++;		
	}
    memcpy(pKey, key,32);

	if (memcmp(&key[0], pKey, keyLength) != 0){
		FPRINT("*****Where is my Key ????");	
	}	
	else
		FPRINT("*****Verify KEY OK!!!");		
}


void HW_CAM_UpdateRollTbl(zd_80211Obj_t *pObj, U16 aid)	
{	
	void *reg = pObj->reg;
	U32 tmpValue;
	
	if (aid >= 32){
		tmpValue = pObj->GetReg(reg, ZD_CAM_ROLL_TB_HIGH);
		tmpValue |= BIT_0 << (aid-32);
		pObj->SetReg(reg, ZD_CAM_ROLL_TB_HIGH, tmpValue);
	}
	else {
		tmpValue = pObj->GetReg(reg, ZD_CAM_ROLL_TB_LOW);
		tmpValue |= (BIT_0 << aid);
		pObj->SetReg(reg, ZD_CAM_ROLL_TB_LOW, tmpValue);
	}	
}


void HW_CAM_ResetRollTbl(zd_80211Obj_t *pObj)	
{	
	void *reg = pObj->reg;
	
        WPADEBUG("ResetRollTbl..\n");	
	pObj->SetReg(reg, ZD_CAM_ROLL_TB_LOW, 0);
	pObj->SetReg(reg, ZD_CAM_ROLL_TB_HIGH, 0);
}	


void HW_CAM_ClearRollTbl(zd_80211Obj_t *pObj, U16 aid)	
{	
	void *reg = pObj->reg;
	U32 tmpValue;

    	WPADEBUG("HW_CAM_ClearRollTbl: aid:%d\n", aid);	
	//update roll table
	if (aid > 32) {
		tmpValue = pObj->GetReg(reg, ZD_CAM_ROLL_TB_HIGH);
        	WPADEBUG("Current ROLL_TB_HIGH=0x%X\n", (unsigned int)tmpValue);
		tmpValue &= ~(BIT_0 << (aid-32)); //set user invalid
		pObj->SetReg(reg, ZD_CAM_ROLL_TB_HIGH, tmpValue);
	}
	else {
		tmpValue = pObj->GetReg(reg, ZD_CAM_ROLL_TB_LOW);
        	WPADEBUG("Current ROLL_TB_LOW=0x%X\n", (unsigned int)tmpValue);
		tmpValue &= ~(BIT_0 << aid); //set user invalid
		pObj->SetReg(reg, ZD_CAM_ROLL_TB_LOW, tmpValue);
	}	
}
void HW_ConfigDynaKey(zd_80211Obj_t *pObj, U16 aid, U8 *pMac, U8 *pKey, U8 keyLength, U8 encryType, U8 change_enc)
{
static u8 skip_set_mac=0;
	//set MAC address
//	int	flags;
	//flags = pObj->EnterCS();
//	HW_CAM_ClearRollTbl(pObj, aid);
        if (change_enc)
        {
            HW_CAM_SetMAC(pObj, aid, pMac);
            HW_CAM_SetEncryType(pObj, aid, encryType);
        }
        HW_CAM_SetKey(pObj, aid, keyLength, pKey);
        HW_CAM_UpdateRollTbl(pObj, aid);
	//pObj->ExitCS(flags);
}

void HW_ConfigStatKey(zd_80211Obj_t *pObj, U8 *pKey, U8 keyLen, U32 startAddr)
{
	int i, j, k, offset;
	U32 tmpKey = 0;
    U16 loopCheck = 0;
	
	j = 0;
	offset = 0;

	while(offset < keyLen){
        // Just a loop check even if it is impossible occur.
        if(loopCheck++ > 100)
        {
            printk("infinite loop occurs in %s\n", __FUNCTION__);
            loopCheck = 0;
            break;
        }

		for (i=offset, k=0; k<4; i++, k++){
			tmpKey |= pKey[i] << ((k%4)*8);
			offset++;
			if (offset == keyLen)
				goto last_part;
		}
		HW_CAM_Write(pObj, startAddr+j, tmpKey);
		j++;
		tmpKey = 0;
	}	

last_part:
	HW_CAM_Write(pObj, startAddr+j, tmpKey);	
}	 


void HW_GetStatKey(zd_80211Obj_t *pObj)
{
	//void *reg = pObj->reg;
	int i, j;
	U8 key[128];
	U32 tmpValue;
	U32 encryType;
	U8	keyLength;
	
	encryType = HW_CAM_Read(pObj, DEFAULT_ENCRY_TYPE);
	switch(encryType){
		case WEP64:
			FPRINT("WEP64 Mode");	

			keyLength = 5;
			break;
		
		case WEP128:
			FPRINT("WEP128 Mode");	
			keyLength = 13;
			break;
		
		case WEP256:
			FPRINT("WEP256 Mode");	
			keyLength = 29;
			break;	
			
		default:
			FPRINT("Not supported Mode");	
			return;	

	}
	
	for (i=0, j=0; i<32; i++){
		tmpValue = HW_CAM_Read(pObj, (STA_KEY_START_ADDR+i));

		key[j] = (U8)(tmpValue);	
		j++;
		key[j] = (U8)(tmpValue >> 8);
		j++;
		key[j] = (U8)(tmpValue >> 16);
		j++;
		key[j] = (U8)(tmpValue >> 24);
		j++;
	}
    
	zd1205_dump_data("Key 1 = ", (U8 *)&key[0], keyLength);
	zd1205_dump_data("Key 2 = ", (U8 *)&key[32], keyLength);
	zd1205_dump_data("Key 3 = ", (U8 *)&key[2*32], keyLength);
	zd1205_dump_data("Key 4 = ", (U8 *)&key[3*32], keyLength);
	return;	
}

/*
void HW_EEPROM_ACCESS(zd_80211Obj_t *pObj, U8 RamAddr, U32 RomAddr, U32 length, U8 bWrite)
{
	void *reg = pObj->reg;
	U32 status;
	U32 access = 0;
	U32 startTime;
	U32 endTime;
	U32 diffTime;
	int count = 0;
		
	if (bWrite){
		FPRINT("Write Access");
	}
	else
		FPRINT("Read Access");	

		
	FPRINT_V("RomAddr", RomAddr);
	FPRINT_V("RamAddr", RamAddr);
	FPRINT_V("Length", length);
	
	if (bWrite){
		access = EEPROM_WRITE_ACCESS;
		//unlock write access
		pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x55aa);
		pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x44bb);
		pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x33cc);
		pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x22dd);
	}	
					
	pObj->SetReg(reg, ZD_EPP_ROM_ADDRESS, RomAddr);
	pObj->SetReg(reg, ZD_EPP_SRAM_ADDRESS, RamAddr);
	pObj->SetReg(reg, ZD_EPP_LENG_DIR, access | length);
	
	startTime = pObj->GetReg(reg, ZD_TSF_LowPart);
	
	pObj->DelayUs(2000);
	status = pObj->GetReg(reg, ZD_EPP_CLOCK_DIV);
	while(status & EEPROM_BUSY_FLAG){
		pObj->DelayUs(1000);
		//FPRINT("EEPROM programming !!!");
		status = pObj->GetReg(reg, ZD_EPP_CLOCK_DIV);
		
		if (count > 500) {
			FPRINT("EEPROM Timeout !!!");
			if (bWrite)
				pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x00);
			return;
		}	
		//len = pObj->GetReg(reg, ZD_EPP_LENG_DIR);
		//FPRINT_V("len", len);
		count++;
	}	
	
	endTime = pObj->GetReg(reg, ZD_TSF_LowPart);
	if (endTime > startTime){
		diffTime = endTime - startTime;
	}
	else {
		diffTime = 0xffffffff + startTime - endTime;
	}		
	
	//FPRINT_V("Processing Time", diffTime);	
	
	printk("\nProcessing Time = %u ms\n", (u32)diffTime/1000);	
	

	//lock write access
	if (bWrite)
		pObj->SetReg(reg, ZD_EPP_KEY_PROT, 0x00);
}	
*/
void HW_EEPROM_ACCESS(zd_80211Obj_t *pObj, U16 RamAddr, U16 RomAddr, U32 length,
U8 bWrite)
{
    void *reg = pObj->reg;
    U32 tmp;
    U32 access = 0;
    tmp = pObj->GetReg(reg, ZD1211_CLOCK_CTRL);
    pObj->SetReg(reg, ZD1211_CLOCK_CTRL, tmp | BIT_0);
    
    if(bWrite) 
        access = BIT_15; 

#ifdef ZD1211B
    if(bWrite)
    {
        pObj->SetReg(reg, 0x863a, 0x55aa);
        pObj->SetReg(reg, 0x8685, 0x44bb);
        pObj->SetReg(reg, 0x861b, 0x33cc);
        pObj->SetReg(reg, 0x8666, 0x22dd);
        pObj->DelayUs(5000);
    }
#endif



    pObj->SetReg(reg, 0x862a, RomAddr);
    pObj->SetReg(reg, 0x862b, RamAddr);
    pObj->SetReg(reg, 0x862c, length | access);

    pObj->DelayUs(5000);
    pObj->SetReg(reg, ZD1211_CLOCK_CTRL, tmp & ~BIT_0);
    

}
/*
void ZD1205_WriteE2P(zd_80211Obj_t *pObj)
{

    u32 tmpvalue;
    int i;
    void *reg = pObj->reg;

    //0x00000000 means the first 2K
    pObj->SetReg(reg,E2P_ADDR_COUNTER,0x00000000);
    //0x8100 -> 8 means write to eeprom
    //       -> 0x100 means 2K
    tmpvalue = pObj->GetReg(reg,E2P_DMA_LENGTH);
    tmpvalue &= 0xFFFF0000;
    tmpvalue |= 0x00008100;
    pObj->SetReg(reg,E2P_DMA_LENGTH,tmpvalue);
    //0x0 means 78.125KHz, 0x1 means 312.5KHz
    pObj->SetReg(reg,E2P_CLOCK,0x00000000);
    //0x55aa->0x44bb->0x33cc->0x22dd means unlock the key
    tmpvalue = pObj->GetReg(reg,E2P_WRITE_PROTECT);
    tmpvalue &= 0xFFFF0000;
    tmpvalue |= 0x000055aa;
    pObj->SetReg(reg,E2P_WRITE_PROTECT,tmpvalue);
    tmpvalue = pObj->GetReg(reg,E2P_WRITE_PROTECT);
    tmpvalue &= 0xFFFF0000;
    tmpvalue |= 0x000044bb;
    pObj->SetReg(reg,E2P_WRITE_PROTECT,tmpvalue);
    tmpvalue = pObj->GetReg(reg,E2P_WRITE_PROTECT);
    tmpvalue &= 0xFFFF0000;
    tmpvalue |= 0x000033cc;
    pObj->SetReg(reg,E2P_WRITE_PROTECT,tmpvalue);
    tmpvalue = pObj->GetReg(reg,E2P_WRITE_PROTECT);
    tmpvalue &= 0xFFFF0000;
    tmpvalue |= 0x000022dd;
    pObj->SetReg(reg,E2P_WRITE_PROTECT,tmpvalue);

    //wait until the DMA busy flag is clear
    tmpvalue = pObj->GetReg(reg,E2P_CLOCK);
    i=0;
    while ( (tmpvalue&0x8000) != 0) {
        pObj->DelayUs(10);
        i++;
        tmpvalue = pObj->GetReg(reg,E2P_CLOCK);
    }
    //lock the key to provide write protection
    //if not lock the key , EEPROM will hang when read it again
    pObj->SetReg(reg,E2P_WRITE_PROTECT,0x0);

}
*/


#endif

